RF_OPTIONAL
if (res[i] == NULL && !(rs[i].flags & RF_OPTIONAL)) {
{ SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
.flags = RF_ACTIVE | RF_OPTIONAL,
.flags = RF_ACTIVE | RF_OPTIONAL,
.flags = RF_ACTIVE | RF_OPTIONAL,
if (bootverbose || (flags & RF_OPTIONAL) == 0) {
(flags & RF_OPTIONAL) != 0 ? "optional" :
if ((flags & RF_OPTIONAL) == 0)
if (bootverbose || (flags & RF_OPTIONAL) == 0) {
(flags & RF_OPTIONAL) != 0 ?
if ((flags & RF_OPTIONAL) == 0)
flags &= ~RF_OPTIONAL;
if ((irq_def->flags & RF_OPTIONAL) != 0)
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */
{ SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_MEMORY, 1, RF_ACTIVE | RF_UNMAPPED | RF_OPTIONAL },
{ SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
if (res[i] == NULL && !(rs[i].flags & RF_OPTIONAL)) {
{ DPAA2_DEV_MCP, MCP_RID(0), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_MCP, MCP_RID(0), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_MCP, MCP_RID(0), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ SYS_RES_MEMORY, MEM_RID(2), RF_ACTIVE | RF_UNMAPPED | RF_OPTIONAL },
{ DPAA2_DEV_MCP, MCP_RID(0), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ SYS_RES_MEMORY, 1, RF_ACTIVE | RF_UNMAPPED | RF_OPTIONAL },
{ DPAA2_DEV_MCP, DPAA2_NI_MCP_RID(0), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(1), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(2), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(3), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(4), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(5), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(6), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(7), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(8), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(9), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(10), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(11), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(12), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(13), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(14), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_IO, DPAA2_NI_IO_RID(15), RF_ACTIVE | RF_SHAREABLE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(1), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(2), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(3), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(4), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(5), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(6), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(7), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(8), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(9), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(10), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(11), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(12), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(13), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(14), RF_ACTIVE | RF_OPTIONAL },
{ DPAA2_DEV_CON, DPAA2_NI_CON_RID(15), RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 8, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 9, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 10, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 11, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 12, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 13, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 14, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 15, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 16, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 17, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 18, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 19, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 20, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 21, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 22, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 23, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 24, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 25, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 26, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 27, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 28, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 29, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 30, RF_ACTIVE | RF_OPTIONAL },
{ SYS_RES_IRQ, 31, RF_ACTIVE | RF_OPTIONAL },
if (res[i] == NULL && !(rs[i].flags & RF_OPTIONAL)) {