RS_NET_INT
&& !(rt->rt_state & RS_NET_INT)) {
RS_NET_SYN | RS_NET_INT, &loop_rts);
if (RT->rt_state & RS_NET_INT) {
state |= (RS_NET_SYN | RS_NET_INT);
{ RS_NET_INT, RS_NET_SYN, "NET_INT" },