Symbol: READ_REG32
sys/dev/qlxgb/qla_hw.c
1714
hw->txr_comp, hw->txr_free, hw->txr_next, READ_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000))));
sys/dev/qlxgb/qla_hw.c
1750
link_state = READ_REG32(ha, Q8_LINK_STATE);
sys/dev/qlxgb/qla_hw.c
437
data = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP);
sys/dev/qlxgb/qla_hw.c
446
cdrp->rsp = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP);
sys/dev/qlxgb/qla_hw.c
447
cdrp->rsp_arg1 = READ_REG32(ha, Q8_NX_CDRP_ARG1);
sys/dev/qlxgb/qla_hw.c
448
cdrp->rsp_arg2 = READ_REG32(ha, Q8_NX_CDRP_ARG2);
sys/dev/qlxgb/qla_hw.c
449
cdrp->rsp_arg3 = READ_REG32(ha, Q8_NX_CDRP_ARG3);
sys/dev/qlxgb/qla_inline.h
139
mac_lo = READ_REG32(ha, mac_crb_addr);
sys/dev/qlxgb/qla_inline.h
140
mac_hi = READ_REG32(ha, (mac_crb_addr + 0x4));
sys/dev/qlxgb/qla_inline.h
63
if ((READ_REG32(ha, sem_reg) & SEM_LOCK_BIT))
sys/dev/qlxgb/qla_inline.h
85
READ_REG32(ha, sem_reg);
sys/dev/qlxgb/qla_inline.h
99
link_speed = READ_REG32(ha, Q8_LINK_SPEED_0);
sys/dev/qlxgb/qla_reg.h
229
#define READ_OFFSET32(ha, off) READ_REG32(ha, off)
sys/dev/qlxgbe/ql_hw.c
1412
data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL);
sys/dev/qlxgbe/ql_hw.c
1447
data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
sys/dev/qlxgbe/ql_hw.c
1450
data = READ_REG32(ha, Q8_FW_MBOX0);
sys/dev/qlxgbe/ql_hw.c
1477
*fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2)));
sys/dev/qlxgbe/ql_hw.c
2860
ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX);
sys/dev/qlxgbe/ql_hw.c
3788
link_state = READ_REG32(ha, Q8_LINK_STATE);
sys/dev/qlxgbe/ql_hw.c
3821
val = READ_REG32(ha, Q8_ASIC_TEMPERATURE);
sys/dev/qlxgbe/ql_hw.c
3836
val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT);
sys/dev/qlxgbe/ql_hw.c
3856
peg_halt_status1 = READ_REG32(ha, Q8_PEG_HALT_STATUS1);
sys/dev/qlxgbe/ql_hw.c
3857
peg_halt_status2 = READ_REG32(ha, Q8_PEG_HALT_STATUS2);
sys/dev/qlxgbe/ql_hw.c
5022
value = READ_REG32(ha, addr);
sys/dev/qlxgbe/ql_inline.h
55
if ((READ_REG32(ha, sem_reg) & BIT_0))
sys/dev/qlxgbe/ql_inline.h
77
READ_REG32(ha, sem_reg);
sys/dev/qlxgbe/ql_inline.h
91
link_speed = READ_REG32(ha, Q8_LINK_SPEED_0);
sys/dev/qlxgbe/ql_ioctl.c
116
u.rv->val = READ_REG32(ha, u.rv->reg);
sys/dev/qlxgbe/ql_isr.c
763
data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
sys/dev/qlxgbe/ql_isr.c
769
data = READ_REG32(ha, Q8_FW_MBOX0);
sys/dev/qlxgbe/ql_isr.c
779
ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
sys/dev/qlxgbe/ql_isr.c
781
data = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
sys/dev/qlxgbe/ql_isr.c
787
data = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
sys/dev/qlxgbe/ql_isr.c
809
data = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
sys/dev/qlxgbe/ql_isr.c
824
ha->hw.aen_mb1 = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
sys/dev/qlxgbe/ql_isr.c
825
ha->hw.aen_mb2 = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
sys/dev/qlxgbe/ql_isr.c
826
ha->hw.aen_mb3 = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
sys/dev/qlxgbe/ql_isr.c
827
ha->hw.aen_mb4 = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
sys/dev/qlxgbe/ql_isr.c
838
ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
sys/dev/qlxgbe/ql_isr.c
839
ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
sys/dev/qlxgbe/ql_isr.c
840
ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
sys/dev/qlxgbe/ql_isr.c
841
ombx[3] = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
sys/dev/qlxgbe/ql_isr.c
842
ombx[4] = READ_REG32(ha, (Q8_FW_MBOX0 + 20));
sys/dev/qlxgbe/ql_isr.c
855
__func__, READ_REG32(ha, (Q8_FW_MBOX0 + 4)));
sys/dev/qlxgbe/ql_isr.c
867
ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
sys/dev/qlxgbe/ql_isr.c
868
ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
sys/dev/qlxgbe/ql_isr.c
869
ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
sys/dev/qlxgbe/ql_misc.c
1241
addr = (uint64_t)(READ_REG32(ha, Q8_BOOTLD_ADDR));
sys/dev/qlxgbe/ql_misc.c
1258
addr = (uint64_t)(READ_REG32(ha, Q8_FW_IMAGE_ADDR));
sys/dev/qlxgbe/ql_misc.c
676
mem_off = (uint64_t)(READ_REG32(ha, Q8_BOOTLD_ADDR));
sys/dev/qlxgbe/ql_misc.c
677
mem_size = READ_REG32(ha, Q8_BOOTLD_SIZE);
sys/dev/qlxgbe/ql_misc.c
728
data = READ_REG32(ha, Q8_CMDPEG_STATE);
sys/dev/qlxgbe/ql_misc.c
73
if (READ_REG32(ha, wnd_reg) == addr)
sys/dev/qlxgbe/ql_misc.c
762
val = READ_REG32(ha, Q8_CMDPEG_STATE);
sys/dev/qlxgbe/ql_misc.c
777
val = READ_REG32(ha, Q8_CMDPEG_STATE);
sys/dev/qlxgbe/ql_misc.c
784
ha->fw_ver_major = READ_REG32(ha, Q8_FW_VER_MAJOR);
sys/dev/qlxgbe/ql_misc.c
785
ha->fw_ver_minor = READ_REG32(ha, Q8_FW_VER_MINOR);
sys/dev/qlxgbe/ql_misc.c
786
ha->fw_ver_sub = READ_REG32(ha, Q8_FW_VER_SUB);
sys/dev/qlxgbe/ql_misc.c
85
*val = READ_REG32(ha, Q8_WILD_CARD);
sys/dev/qlxge/qls_dump.c
1221
lo_val = READ_REG32(ha,\
sys/dev/qlxge/qls_dump.c
1233
hi_val = READ_REG32(ha,\
sys/dev/qlxge/qls_dump.c
1424
r_idx = READ_REG32(ha, Q81_CTL_ROUTING_INDEX);
sys/dev/qlxge/qls_dump.c
1426
r_data = READ_REG32(ha, Q81_CTL_ROUTING_DATA);
sys/dev/qlxge/qls_dump.c
1533
READ_REG32(ha, \
sys/dev/qlxge/qls_dump.c
1536
result_data = READ_REG32(ha,\
sys/dev/qlxge/qls_dump.c
1558
*buf = READ_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD);
sys/dev/qlxge/qls_dump.c
1564
*buf = READ_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD);
sys/dev/qlxge/qls_dump.c
1620
READ_REG32(ha, i * sizeof(uint32_t));
sys/dev/qlxge/qls_dump.c
1632
READ_REG32(ha, i * sizeof(uint32_t));
sys/dev/qlxge/qls_dump.c
380
data = READ_REG32(ha, reg);
sys/dev/qlxge/qls_dump.c
412
*data = READ_REG32(ha, Q81_CTL_PROC_DATA);
sys/dev/qlxge/qls_dump.c
618
*data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA);
sys/dev/qlxge/qls_dump.c
808
data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
sys/dev/qlxge/qls_dump.c
829
data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
sys/dev/qlxge/qls_dump.c
851
*buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE);
sys/dev/qlxge/qls_dump.c
872
*data = READ_REG32(ha, Q81_CTL_XGMAC_DATA);
sys/dev/qlxge/qls_hw.c
1310
link_state = READ_REG32(ha, Q81_CTL_STATUS);
sys/dev/qlxge/qls_hw.c
1760
data32 = READ_REG32(ha, Q81_CTL_FLASH_ADDR);
sys/dev/qlxge/qls_hw.c
1798
*data = READ_REG32(ha, Q81_CTL_FLASH_DATA);
sys/dev/qlxge/qls_hw.c
1889
data = READ_REG32(ha, Q81_CTL_SEMAPHORE);
sys/dev/qlxge/qls_hw.c
1914
data32 = READ_REG32(ha, Q81_CTL_PROC_ADDR);
sys/dev/qlxge/qls_hw.c
1953
*data = READ_REG32(ha, Q81_CTL_PROC_DATA);
sys/dev/qlxge/qls_hw.c
1998
data = READ_REG32(ha, Q81_CTL_RESET);
sys/dev/qlxge/qls_hw.c
2039
data = READ_REG32(ha, Q81_CTL_STATUS);
sys/dev/qlxge/qls_hw.c
2141
data32 = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
sys/dev/qlxge/qls_hw.c
2179
data32 = READ_REG32(ha, Q81_CTL_STATUS);
sys/dev/qlxge/qls_hw.c
220
data32 = READ_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX);
sys/dev/qlxge/qls_hw.c
2393
data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
sys/dev/qlxge/qls_hw.c
359
data32 = READ_REG32(ha, Q81_CTL_ROUTING_INDEX);
sys/dev/qlxge/qls_hw.c
901
ha->rev_id = READ_REG32(ha, Q81_CTL_REV_ID);
sys/dev/qlxge/qls_hw.c
960
data32 = READ_REG32(ha, Q81_CTL_CONFIG);
sys/dev/qlxge/qls_isr.c
373
status = READ_REG32(ha, Q81_CTL_STATUS);
sys/dev/qlxge/qls_isr.c
384
status = READ_REG32(ha, Q81_CTL_INTR_STATUS1);