RD2
reg = RD2(sc, WDOG_CR_REG);
reg = RD2(sc, WDOG_MCR_REG);
WR2(sc, WDOG_CR_REG, WDOG_CR_WDT | RD2(sc, WDOG_CR_REG));
if (RD2(sc, WDOG_MCR_REG) & WDOG_MCR_PDE)
while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
status = RD2(sc, CDNC_I2C_ISR) & ~RD2(sc, CDNC_I2C_IMR);
statr = RD2(sc, CDNC_I2C_SR);
msg->buf[idx++] = RD2(sc, CDNC_I2C_DATA);
hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
val16 = RD2(slot, SDHCI_ACMD12_ERR);
RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
clk = RD2(slot, SDHCI_CLOCK_CONTROL);
clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
slot->version = (RD2(slot, SDHCI_HOST_VERSION)