sys/arm/broadcom/bcm2835/bcm2835_sdhost.c

827

val1 = RD1(sc, HC_POWER);

sys/arm/nvidia/as3722.c

197

rv = RD1(sc, AS3722_ASIC_ID1, &reg);

sys/arm/nvidia/as3722.c

206

rv = RD1(sc, AS3722_ASIC_ID2, &sc->chip_rev);

sys/arm/nvidia/as3722_gpio.c

488

rv = RD1(sc, AS3722_GPIO_SIGNAL_OUT, &tmp);

sys/arm/nvidia/as3722_gpio.c

490

rv = RD1(sc, AS3722_GPIO_SIGNAL_IN, &tmp);

sys/arm/nvidia/as3722_gpio.c

513

rv = RD1(sc, AS3722_GPIO_SIGNAL_OUT, &tmp);

sys/arm/nvidia/as3722_gpio.c

559

rv = RD1(sc, AS3722_GPIO0_CONTROL + i, &pin->pin_ctrl_reg);

sys/arm/nvidia/as3722_regulators.c

389

rv = RD1(sc->base_sc, sc->def->volt_reg, sel);

sys/arm/nvidia/as3722_regulators.c

418

rv = RD1(sc->base_sc, AS3722_FUSE7, &val);

sys/arm64/nvidia/tegra210/max77620.c

257

rv = RD1(sc, MAX77620_REG_CID0 + i , buf + i);

sys/arm64/nvidia/tegra210/max77620.c

342

RD1(sc, MAX77620_REG_INTENLBT, &intenlbt);

sys/arm64/nvidia/tegra210/max77620.c

343

RD1(sc, MAX77620_REG_INTLBT, &intlbt);

sys/arm64/nvidia/tegra210/max77620.c

345

RD1(sc, MAX77620_REG_IRQTOP, &irqtop);

sys/arm64/nvidia/tegra210/max77620.c

346

RD1(sc, MAX77620_REG_IRQTOPM, &irqtopm);

sys/arm64/nvidia/tegra210/max77620.c

347

RD1(sc, MAX77620_REG_IRQSD, &irqsd);

sys/arm64/nvidia/tegra210/max77620.c

348

RD1(sc, MAX77620_REG_IRQMASKSD, &irqmasksd);

sys/arm64/nvidia/tegra210/max77620.c

349

RD1(sc, MAX77620_REG_IRQ_LVL2_L0_7, &irq_lvl2_l0_7);

sys/arm64/nvidia/tegra210/max77620.c

350

RD1(sc, MAX77620_REG_IRQ_MSK_L0_7, &irq_msk_l0_7);

sys/arm64/nvidia/tegra210/max77620.c

351

RD1(sc, MAX77620_REG_IRQ_LVL2_L8, &irq_lvl2_l8);

sys/arm64/nvidia/tegra210/max77620.c

352

RD1(sc, MAX77620_REG_IRQ_MSK_L8, &irq_msk_l8);

sys/arm64/nvidia/tegra210/max77620.c

353

RD1(sc, MAX77620_REG_IRQ_LVL2_GPIO, &irq_lvl2_gpio);

sys/arm64/nvidia/tegra210/max77620.c

354

RD1(sc, MAX77620_REG_ONOFFIRQ, &onoffirq);

sys/arm64/nvidia/tegra210/max77620.c

355

RD1(sc, MAX77620_REG_ONOFFIRQM, &onoffirqm);

sys/arm64/nvidia/tegra210/max77620_gpio.c

211

rv = RD1(sc, pin->reg, &reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

446

rv = RD1(sc, pin->reg, &reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

527

rv = RD1(sc, pin->reg, &reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

618

rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp);

sys/arm64/nvidia/tegra210/max77620_gpio.c

643

rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp);

sys/arm64/nvidia/tegra210/max77620_gpio.c

679

rv = RD1(sc, MAX77620_REG_PUE_GPIO, &sc->gpio_reg_pue);

sys/arm64/nvidia/tegra210/max77620_gpio.c

685

rv = RD1(sc, MAX77620_REG_PDE_GPIO, &sc->gpio_reg_pde);

sys/arm64/nvidia/tegra210/max77620_gpio.c

691

rv = RD1(sc, MAX77620_REG_AME_GPIO, &sc->gpio_reg_ame);

sys/arm64/nvidia/tegra210/max77620_regulators.c

365

rv = RD1(sc->base_sc, sc->def->volt_reg, sel);

sys/arm64/nvidia/tegra210/max77620_regulators.c

400

rv = RD1(sc->base_sc, sc->def->fps_reg, &val);

sys/arm64/nvidia/tegra210/max77620_regulators.c

460

rv = RD1(sc->base_sc, sc->def->pwr_mode_reg, &val);

sys/arm64/nvidia/tegra210/max77620_regulators.c

487

rv = RD1(sc->base_sc, sc->def->cfg_reg, &val);

sys/arm64/nvidia/tegra210/max77620_regulators.c

557

RD1(sc->base_sc, sc->def->volt_reg, &val1);

sys/arm64/nvidia/tegra210/max77620_regulators.c

558

RD1(sc->base_sc, sc->def->cfg_reg, &val2);

sys/arm64/nvidia/tegra210/max77620_regulators.c

559

RD1(sc->base_sc, sc->def->fps_reg, &val3);

sys/dev/hdmi/dwc_hdmi.c

186

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

197

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

208

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

219

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

230

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

241

reg = RD1(sc, HDMI_PHY_CONF0);

sys/dev/hdmi/dwc_hdmi.c

252

val = RD1(sc, HDMI_PHY_TST0);

sys/dev/hdmi/dwc_hdmi.c

268

val = RD1(sc, HDMI_FC_INVIDCONF);

sys/dev/hdmi/dwc_hdmi.c

372

val = RD1(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;

sys/dev/hdmi/dwc_hdmi.c

379

val = RD1(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;

sys/dev/hdmi/dwc_hdmi.c

424

clkdis = RD1(sc, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE;

sys/dev/hdmi/dwc_hdmi.c

467

val = RD1(sc, HDMI_AUD_CTS3);

sys/dev/hdmi/dwc_hdmi.c

471

val = RD1(sc, HDMI_AUD_CONF0);

sys/dev/hdmi/dwc_hdmi.c

478

val = RD1(sc, HDMI_AUD_CONF1);

sys/dev/hdmi/dwc_hdmi.c

494

val = RD1(sc, HDMI_MC_CLKDIS);

sys/dev/hdmi/dwc_hdmi.c

515

val = RD1(sc, HDMI_VP_STUFF);

sys/dev/hdmi/dwc_hdmi.c

520

val = RD1(sc, HDMI_VP_CONF);

sys/dev/hdmi/dwc_hdmi.c

527

val = RD1(sc, HDMI_VP_STUFF);

sys/dev/hdmi/dwc_hdmi.c

535

val = RD1(sc, HDMI_VP_CONF);

sys/dev/hdmi/dwc_hdmi.c

544

val = RD1(sc, HDMI_VP_CONF);

sys/dev/hdmi/dwc_hdmi.c

553

val = RD1(sc, HDMI_VP_CONF);

sys/dev/hdmi/dwc_hdmi.c

565

val = RD1(sc, HDMI_VP_STUFF);

sys/dev/hdmi/dwc_hdmi.c

572

val = RD1(sc, HDMI_VP_CONF);

sys/dev/hdmi/dwc_hdmi.c

611

val = RD1(sc, HDMI_A_HDCPCFG0);

sys/dev/hdmi/dwc_hdmi.c

617

val = RD1(sc, HDMI_A_VIDPOLCFG);

sys/dev/hdmi/dwc_hdmi.c

623

val = RD1(sc, HDMI_A_HDCPCFG1);

sys/dev/hdmi/dwc_hdmi.c

715

stat = RD1(sc, HDMI_IH_PHY_STAT0);

sys/dev/hdmi/dwc_hdmi.c

738

RD1(sc, HDMI_DESIGN_ID), RD1(sc, HDMI_REVISION_ID),

sys/dev/hdmi/dwc_hdmi.c

739

RD1(sc, HDMI_PRODUCT_ID0), RD1(sc, HDMI_PRODUCT_ID1));

sys/dev/hdmi/dwc_hdmi.c

77

val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) &

sys/dev/hdmi/dwc_hdmi.c

84

val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) &

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

428

RD1(sc, CDNC_I2C_TRANS_SIZE) - 1);

sys/dev/iicbus/pmic/act8846_regulator.c

245

rv = RD1(sc->base_sc, sc->def->voltage_reg, sel);

sys/dev/sdhci/sdhci.c

1286

while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {

sys/dev/sdhci/sdhci.c

1297

while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {

sys/dev/sdhci/sdhci.c

237

RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));

sys/dev/sdhci/sdhci.c

239

RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));

sys/dev/sdhci/sdhci.c

241

RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));

sys/dev/sdhci/sdhci.c

243

RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));

sys/dev/sdhci/sdhci.c

251

RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));

sys/dev/sdhci/sdhci.c

548

if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)

sys/dev/sdhci/sdhci.c

552

if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))