sys/dev/msk/if_msk.c

3437

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);

sys/dev/msk/if_msk.c

3442

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);

sys/dev/msk/if_msk.c

3932

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);

sys/dev/msk/if_msk.c

3933

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);

sys/dev/msk/if_msk.c

3934

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);

sys/dev/msk/if_msk.c

3935

CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);

sys/dev/msk/if_msk.c

3940

CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),

sys/dev/msk/if_msk.c

3950

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),

sys/dev/msk/if_msk.c

3956

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);

sys/dev/msk/if_msk.c

3957

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);

sys/dev/msk/if_msk.c

3958

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);

sys/dev/msk/if_msk.c

3959

CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);

sys/dev/msk/if_msk.c

3963

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);

sys/dev/msk/if_msk.c

3977

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);

sys/dev/msk/if_msk.c

4151

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);

sys/dev/msk/if_msk.c

4152

val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));

sys/dev/msk/if_msk.c

4155

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),

sys/dev/msk/if_msk.c

4157

val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));

sys/dev/msk/if_msk.c

4176

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),

sys/dev/msk/if_msk.c

4212

CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),