sys/arm/ti/ti_adc.c

153

ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);

sys/arm/ti/ti_adc.c

160

ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));

sys/arm/ti/ti_adc.c

163

count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;

sys/arm/ti/ti_adc.c

165

(void)ADC_READ4(sc, ADC_FIFO0DATA);

sys/arm/ti/ti_adc.c

166

count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;

sys/arm/ti/ti_adc.c

169

count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;

sys/arm/ti/ti_adc.c

171

(void)ADC_READ4(sc, ADC_FIFO1DATA);

sys/arm/ti/ti_adc.c

172

count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;

sys/arm/ti/ti_adc.c

198

if (enabled != ADC_READ4(sc, ADC_STEPENABLE))

sys/arm/ti/ti_adc.c

216

val = ADC_READ4(sc, reg);

sys/arm/ti/ti_adc.c

264

reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;

sys/arm/ti/ti_adc.c

338

reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;

sys/arm/ti/ti_adc.c

396

count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;

sys/arm/ti/ti_adc.c

398

data = ADC_READ4(sc, ADC_FIFO0DATA);

sys/arm/ti/ti_adc.c

405

count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;

sys/arm/ti/ti_adc.c

434

count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;

sys/arm/ti/ti_adc.c

440

data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK;

sys/arm/ti/ti_adc.c

441

count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;

sys/arm/ti/ti_adc.c

507

rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW);

sys/arm/ti/ti_adc.c

508

status = ADC_READ4(sc, ADC_IRQSTATUS);

sys/arm/ti/ti_adc.c

660

val = ADC_READ4(sc, ADC_IDLECONFIG);

sys/arm/ti/ti_adc.c

845

rev = ADC_READ4(sc, ti_sysc_get_rev_address_offset_host(device_get_parent(dev)));

sys/arm/ti/ti_adc.c

855

reg = ADC_READ4(sc, ADC_CTRL);