Symbol: PLL_BASE_DIVN_SHIFT
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
497
*n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
509
val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
734
reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
921
reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);