Symbol: PLL_BASE_DIVM_SHIFT
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
496
*m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
508
val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
733
reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
920
reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);