Symbol: PLLU_BASE
sys/arm/nvidia/tegra124/tegra124_car.c
246
GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22),
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
312
.base_reg = PLLU_BASE,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
396
.base_reg = PLLU_BASE,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
510
GATE(0, "pllU_480", "pllU", PLLU_BASE, 22),
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
511
GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23),
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
512
GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25),
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
551
DIV_TB(0, "pllU_out0", "pllU", PLLU_BASE, 16, 5, tegra210_pll_pdiv_tbl),