PLLP_OUTB
GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
GATE_PLL(0, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8),
DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24),
GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
GATE_PLL(TEGRA210_CLK_PLL_P_OUT4, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8),
DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24),