sys/arm/nvidia/tegra124/tegra124_clk_pll.c

586

RD4(sc, PLLE_SS_CNTL, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

588

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

602

RD4(sc, PLLE_SS_CNTL, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

607

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

610

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

614

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

779

RD4(sc, PLLE_SS_CNTL, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

781

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

793

RD4(sc, PLLE_SS_CNTL, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

802

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

805

WR4(sc, PLLE_SS_CNTL, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

809

WR4(sc, PLLE_SS_CNTL, reg);