sys/arm/nvidia/tegra124/tegra124_car.c

229

MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),

sys/arm/nvidia/tegra124/tegra124_car.c

230

MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),

sys/arm/nvidia/tegra124/tegra124_car.c

256

GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),

sys/arm/nvidia/tegra124/tegra124_car.c

257

GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

570

RD4(sc, PLLE_AUX, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

573

WR4(sc, PLLE_AUX, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

622

RD4(sc, PLLE_AUX, &reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

627

WR4(sc, PLLE_AUX, reg);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

631

WR4(sc, PLLE_AUX, reg);

sys/arm64/nvidia/tegra210/tegra210_car.c

247

GATE(TEGRA210_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),

sys/arm64/nvidia/tegra210/tegra210_car.c

248

GATE(TEGRA210_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

494

MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

495

MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

763

RD4(sc, PLLE_AUX, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

766

WR4(sc, PLLE_AUX, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

817

RD4(sc, PLLE_AUX, &reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

822

WR4(sc, PLLE_AUX, reg);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

826

WR4(sc, PLLE_AUX, reg);