Symbol: PLLD2_BASE
sys/arm/nvidia/tegra124/tegra124_car.c
226
MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
sys/arm/nvidia/tegra124/tegra124_car.c
234
MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1),
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
333
.base_reg = PLLD2_BASE,
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
337
.iddq_reg = PLLD2_BASE,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
421
.base_reg = PLLD2_BASE,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
424
.iddq_reg = PLLD2_BASE,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
491
MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),