Symbol: PLLC4_BASE
sys/arm/nvidia/tegra124/tegra124_car.c
228
MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
279
.base_reg = PLLC4_BASE,
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
283
.iddq_reg = PLLC4_BASE,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
344
.base_reg = PLLC4_BASE,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
347
.iddq_reg = PLLC4_BASE,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
493
MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
559
"pllC4_out0", "pllC4", PLLC4_BASE, 19, 5, tegra210_pll_pdiv_tbl),