sys/arm/nvidia/tegra124/tegra124_car.c

184

PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */

sys/arm/nvidia/tegra124/tegra124_car.c

185

PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};

sys/arm/nvidia/tegra124/tegra124_car.c

186

PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"};

sys/arm/nvidia/tegra124/tegra124_car.c

187

PLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"};

sys/arm/nvidia/tegra124/tegra124_car.c

188

PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"};

sys/arm/nvidia/tegra124/tegra124_car.c

189

PLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"};

sys/arm/nvidia/tegra124/tegra124_clk_per.c

100

PLIST(mux_a_N_audio3_N_p_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

103

PLIST(mux_a_N_audio4_N_p_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

106

PLIST(mux_a_clks_p_clkm_e) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

109

PLIST(mux_a_c2_c_c3_p_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

113

PLIST(mux_m_c_p_a_c2_c3) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

116

PLIST(mux_m_c_p_a_c2_c3_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

119

PLIST(mux_m_c_p_a_c2_c3_clkm_c4) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

122

PLIST(mux_m_c_p_clkm_mud_c2_c3) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

125

PLIST(mux_m_c_p_clkm_mud_c2_c3_cud) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

129

PLIST(mux_m_c2_c_c3_p_N_a) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

132

PLIST(mux_m_c2_c_c3_p_N_a_c4) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

136

PLIST(mux_p_N_c_N_N_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

139

PLIST(mux_p_N_c_N_m_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

142

PLIST(mux_p_c_c2_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

144

PLIST(mux_p_c2_c_c3_m) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

147

PLIST(mux_p_c2_c_c3_m_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

150

PLIST(mux_p_c2_c_c3_m_e_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

153

PLIST(mux_p_c2_c_c3_m_a_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

156

PLIST(mux_p_c2_c_c3_m_clks_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

159

PLIST(mux_p_c2_c_c3_clks_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

162

PLIST(mux_p_c2_c_c3_clkm_N_clks) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

165

PLIST(mux_p_clkm_clks_E) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

167

PLIST(mux_p_m_d_a_c_d2_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

171

PLIST(mux_clkm_N_u48_N_p_N_u480) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

174

PLIST(mux_clkm_p_c2_c_c3_refre) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

177

PLIST(mux_clkm_refe_clks_u480_c_c2_c3_oscdiv) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

181

PLIST(mux_sep_audio) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

88

PLIST(mux_a_N_audio_N_p_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

91

PLIST(mux_a_N_audio0_N_p_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

94

PLIST(mux_a_N_audio1_N_p_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_per.c

97

PLIST(mux_a_N_audio2_N_p_N_clkm) =

sys/arm/nvidia/tegra124/tegra124_clk_super.c

66

PLIST(cclk_g_parents) = {

sys/arm/nvidia/tegra124/tegra124_clk_super.c

73

PLIST(cclk_lp_parents) = {

sys/arm/nvidia/tegra124/tegra124_clk_super.c

81

PLIST(sclk_parents) = {

sys/arm64/nvidia/tegra210/tegra210_car.c

185

PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60", "pc_xusb_ss" };

sys/arm64/nvidia/tegra210/tegra210_car.c

186

PLIST(mux_xusb_ssp) = {"xusb_ss", "osc_div_clk"};

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

101

PLIST(mux_N_c2_c_c3_p_N_a) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

104

PLIST(mux_N_c2_c_c3_p_clkm_a1_c4) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

107

PLIST(mux_N_c2_c_c3_p_N_a1_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

111

PLIST(mux_a_N_audio_N_p_N_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

114

PLIST(mux_a_N_audio0_N_p_N_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

117

PLIST(mux_a_N_audio1_N_p_N_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

120

PLIST(mux_a_N_audio2_N_p_N_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

123

PLIST(mux_a_N_audio3_N_p_N_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

126

PLIST(mux_a_N_audio4_N_p_N_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

129

PLIST(mux_a_audiod1_p_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

132

PLIST(mux_a_audiod2_p_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

135

PLIST(mux_a_audiod3_p_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

138

PLIST(mux_a_c4_c_c4o1_p_N_clkm_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

142

PLIST(mux_a_clks_p_clkm_e) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

145

PLIST(mux_c4o1_c2_c_c4_p_clkm_a_c4) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

149

PLIST(mux_m_c_p_clkm_mud_mbud_mb_pud) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

152

PLIST(mux_p_N_N_c4o2_c4o1_N_clkm_c4) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

155

PLIST(mux_p_N_c_c4_c4o1_c4o2_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

158

PLIST(mux_p_N_c_c4_N_c4o1_clkm_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

161

PLIST(mux_p_N_d_N_N_d2_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

164

PLIST(mux_p_N_clkm_N_clks_N_E) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

167

PLIST(mux_p_c_c2_N_c2_N_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

170

PLIST(mux_p_co1_c_N_c4o2_c4o1_clkm_c4) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

173

PLIST(mux_p_c2_c_c3_N_a1_clkm_c4) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

176

PLIST(mux_p_c2_c_c3_N_N_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

179

PLIST(mux_p_c2_c_c3_m_e_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

182

PLIST(mux_p_c2_c_c4_N_c4o1_clkm_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

185

PLIST(mux_p_c2_c_c4_a_c4o1_clkm_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

188

PLIST(mux_p_c2_c_c4o2_c4o1_clks_clkm_c4) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

192

PLIST(mux_p_c2_c_c4_c4o1_clkm_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

195

PLIST(mux_p_c2_c_c4_clkm_c4o1_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

198

PLIST(mux_p_c2_c_c4_clks_c4o1_clkm_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

201

PLIST(mux_p_c2_c_c4_clkm_c4o1_clks_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

204

PLIST(mux_p_c2_refe1_c3_m_a1_clkm_C4) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

207

PLIST(mux_p_c4_c_c4o1_N_c4o2_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

210

PLIST(mux_p_m_d_a_c_d2_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

213

PLIST(mux_p_po3_clkm_clks_a) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

217

PLIST(mux_po3_c_c2_clkm_p_c4_c4o1_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

221

PLIST(mux_clkm_p_N_N_N_refre) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

224

PLIST(mux_clkm_N_u48_N_p_N_u480) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

227

PLIST(mux_clkm_refe_clks_u480) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

231

PLIST(mux_sep_audio) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

82

PLIST(mux_N_N_c_N_p_N_a) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

85

PLIST(mux_N_N_p_N_N_N_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

88

PLIST(mux_N_c_p_a1_c2_c3_clkm) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

91

PLIST(mux_N_c_p_a1_c2_c3_clkm_c4) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

94

PLIST(mux_N_c_p_clkm_N_c4_c4o1_c4o1) =

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

97

PLIST(mux_N_c_p_clkm_N_c4_c4o1_c4o2) =

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

486

PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

487

PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

488

PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out0"};

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

60

PLIST(cclk_g_parents) = {

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

67

PLIST(cclk_lp_parents) = {

sys/arm64/nvidia/tegra210/tegra210_clk_super.c

74

PLIST(sclk_parents) = {

sys/dev/clk/rockchip/rk3288_cru.c

527

PLIST(pll_src_p) = {"xin24m", "xin24m", "xin32k"};

sys/dev/clk/rockchip/rk3288_cru.c

528

PLIST(armclk_p)= {"apll_core", "gpll_core"};

sys/dev/clk/rockchip/rk3288_cru.c

529

PLIST(ddrphy_p) = {"dpll_ddr", "gpll_ddr"};

sys/dev/clk/rockchip/rk3288_cru.c

530

PLIST(aclk_cpu_p) = {"cpll_aclk_cpu", "gpll_aclk_cpu"};

sys/dev/clk/rockchip/rk3288_cru.c

532

PLIST(cpll_gpll_p) = {"cpll", "gpll"};

sys/dev/clk/rockchip/rk3288_cru.c

533

PLIST(npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};

sys/dev/clk/rockchip/rk3288_cru.c

534

PLIST(cpll_gpll_npll_p) = {"cpll", "gpll", "npll"};

sys/dev/clk/rockchip/rk3288_cru.c

535

PLIST(cpll_gpll_usb480m_p)= {"cpll", "gpll", "usbphy480m_src"};

sys/dev/clk/rockchip/rk3288_cru.c

536

PLIST(cpll_gpll_usb480m_npll_p) = {"cpll", "gpll", "usbphy480m_src", "npll"};

sys/dev/clk/rockchip/rk3288_cru.c

538

PLIST(mmc_p) = {"cpll", "gpll", "xin24m", "xin24m"};

sys/dev/clk/rockchip/rk3288_cru.c

539

PLIST(i2s_pre_p) = {"i2s_src", "i2s_frac", "ext_i2s", "xin12m"};

sys/dev/clk/rockchip/rk3288_cru.c

540

PLIST(i2s_clkout_p) = {"i2s_pre", "xin12m"};

sys/dev/clk/rockchip/rk3288_cru.c

541

PLIST(spdif_p) = {"spdif_pre", "spdif_frac", "xin12m"};

sys/dev/clk/rockchip/rk3288_cru.c

542

PLIST(spdif_8ch_p) = {"spdif_8ch_pre", "spdif_8ch_frac", "xin12m"};

sys/dev/clk/rockchip/rk3288_cru.c

543

PLIST(uart0_p) = {"uart0_src", "uart0_frac", "xin24m"};

sys/dev/clk/rockchip/rk3288_cru.c

544

PLIST(uart1_p) = {"uart1_src", "uart1_frac", "xin24m"};

sys/dev/clk/rockchip/rk3288_cru.c

545

PLIST(uart2_p) = {"uart2_src", "uart2_frac", "xin24m"};

sys/dev/clk/rockchip/rk3288_cru.c

546

PLIST(uart3_p) = {"uart3_src", "uart3_frac", "xin24m"};

sys/dev/clk/rockchip/rk3288_cru.c

547

PLIST(uart4_p) = {"uart4_src", "uart4_frac", "xin24m"};

sys/dev/clk/rockchip/rk3288_cru.c

548

PLIST(vip_out_p) = {"vip_src", "xin24m"};

sys/dev/clk/rockchip/rk3288_cru.c

549

PLIST(mac_p) = {"mac_pll_src", "ext_gmac"};

sys/dev/clk/rockchip/rk3288_cru.c

550

PLIST(hsadcout_p) = {"hsadc_src", "ext_hsadc"};

sys/dev/clk/rockchip/rk3288_cru.c

551

PLIST(edp_24m_p) = {"ext_edp_24m", "xin24m"};

sys/dev/clk/rockchip/rk3288_cru.c

552

PLIST(tspout_p) = {"cpll", "gpll", "npll", "xin27m"};

sys/dev/clk/rockchip/rk3288_cru.c

553

PLIST(wifi_p) = {"cpll", "gpll"};

sys/dev/clk/rockchip/rk3288_cru.c

554

PLIST(usbphy480m_p) = {"sclk_otgphy1_480m", "sclk_otgphy2_480m", "sclk_otgphy0_480m"};

sys/dev/clk/rockchip/rk3328_cru.c

639

PLIST(pll_src_p) = {"xin24m"};

sys/dev/clk/rockchip/rk3328_cru.c

640

PLIST(xin24m_rtc32k_p) = {"xin24m", "clk_rtc32k"};

sys/dev/clk/rockchip/rk3328_cru.c

642

PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};

sys/dev/clk/rockchip/rk3328_cru.c

643

PLIST(pll_src_cpll_gpll_apll_p) = {"cpll", "gpll", "apll"};

sys/dev/clk/rockchip/rk3328_cru.c

644

PLIST(pll_src_cpll_gpll_xin24m_p) = {"cpll", "gpll", "xin24m", "xin24m" /* Dummy */};

sys/dev/clk/rockchip/rk3328_cru.c

645

PLIST(pll_src_cpll_gpll_usb480m_p) = {"cpll", "gpll", "usb480m"};

sys/dev/clk/rockchip/rk3328_cru.c

646

PLIST(pll_src_cpll_gpll_hdmiphy_p) = {"cpll", "gpll", "hdmi_phy"};

sys/dev/clk/rockchip/rk3328_cru.c

647

PLIST(pll_src_cpll_gpll_hdmiphy_usb480m_p) = {"cpll", "gpll", "hdmi_phy", "usb480m"};

sys/dev/clk/rockchip/rk3328_cru.c

648

PLIST(pll_src_apll_gpll_dpll_npll_p) = {"apll", "gpll", "dpll", "npll"};

sys/dev/clk/rockchip/rk3328_cru.c

649

PLIST(pll_src_cpll_gpll_xin24m_usb480m_p) = {"cpll", "gpll", "xin24m", "usb480m"};

sys/dev/clk/rockchip/rk3328_cru.c

650

PLIST(mux_ref_usb3otg_p) = { "xin24m", "clk_usb3_otg0_ref" };

sys/dev/clk/rockchip/rk3328_cru.c

651

PLIST(mux_mac2io_p) = { "clk_mac2io_src", "gmac_clkin" };

sys/dev/clk/rockchip/rk3328_cru.c

652

PLIST(mux_mac2io_ext_p) = { "clk_mac2io", "gmac_clkin" };

sys/dev/clk/rockchip/rk3328_cru.c

653

PLIST(mux_mac2phy_p) = { "clk_mac2phy_src", "phy_50m_out" };

sys/dev/clk/rockchip/rk3328_cru.c

654

PLIST(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", "xin12m", "xin12m" };

sys/dev/clk/rockchip/rk3328_cru.c

655

PLIST(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s1", "xin12m" };

sys/dev/clk/rockchip/rk3328_cru.c

656

PLIST(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s2", "xin12m" };

sys/dev/clk/rockchip/rk3328_cru.c

657

PLIST(mux_dclk_lcdc_p) = {"hdmiphy", "vop_dclk_src"};

sys/dev/clk/rockchip/rk3328_cru.c

658

PLIST(mux_hdmiphy_p) = {"hdmi_phy", "xin24m"};

sys/dev/clk/rockchip/rk3328_cru.c

659

PLIST(mux_usb480m_p) = {"usb480m_phy", "xin24m"};

sys/dev/clk/rockchip/rk3328_cru.c

660

PLIST(mux_uart0_p) = {"clk_uart0_div", "clk_uart0_frac", "xin24m", "xin24m"};

sys/dev/clk/rockchip/rk3328_cru.c

661

PLIST(mux_uart1_p) = {"clk_uart1_div", "clk_uart1_frac", "xin24m", "xin24m"};

sys/dev/clk/rockchip/rk3328_cru.c

662

PLIST(mux_uart2_p) = {"clk_uart2_div", "clk_uart2_frac", "xin24m", "xin24m"};

sys/dev/clk/rockchip/rk3328_cru.c

663

PLIST(mux_spdif_p) = {"clk_spdif_div", "clk_spdif_frac", "xin12m", "xin12m"};

sys/dev/clk/rockchip/rk3328_cru.c

664

PLIST(mux_cif_p) = {"clk_cif_pll", "xin24m"};

sys/dev/clk/rockchip/rk3399_cru.c

697

PLIST(pll_src_p) = {"xin24m", "xin32k"};

sys/dev/clk/rockchip/rk3399_cru.c

699

PLIST(armclkl_p) = {"clk_core_l_lpll_src", "clk_core_l_bpll_src",

sys/dev/clk/rockchip/rk3399_cru.c

701

PLIST(armclkb_p) = {"clk_core_b_lpll_src", "clk_core_b_bpll_src",

sys/dev/clk/rockchip/rk3399_cru.c

703

PLIST(ddrclk_p) = {"clk_ddrc_lpll_src", "clk_ddrc_bpll_src",

sys/dev/clk/rockchip/rk3399_cru.c

705

PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"};

sys/dev/clk/rockchip/rk3399_cru.c

706

PLIST(pll_src_cpll_gpll_ppll_p) = {"cpll", "gpll", "ppll"};

sys/dev/clk/rockchip/rk3399_cru.c

707

PLIST(pll_src_cpll_gpll_upll_p) = {"cpll", "gpll", "upll"};

sys/dev/clk/rockchip/rk3399_cru.c

708

PLIST(pll_src_npll_cpll_gpll_p) = {"npll", "cpll", "gpll"};

sys/dev/clk/rockchip/rk3399_cru.c

709

PLIST(pll_src_cpll_gpll_npll_npll_p) = {"cpll", "gpll", "npll", "npll"};

sys/dev/clk/rockchip/rk3399_cru.c

710

PLIST(pll_src_cpll_gpll_npll_ppll_p) = {"cpll", "gpll", "npll", "ppll" };

sys/dev/clk/rockchip/rk3399_cru.c

711

PLIST(pll_src_cpll_gpll_npll_24m_p) = {"cpll", "gpll", "npll", "xin24m" };

sys/dev/clk/rockchip/rk3399_cru.c

712

PLIST(pll_src_cpll_gpll_npll_usbphy480m_p)= {"cpll", "gpll", "npll", "clk_usbphy_480m" };

sys/dev/clk/rockchip/rk3399_cru.c

713

PLIST(pll_src_ppll_cpll_gpll_npll_upll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };

sys/dev/clk/rockchip/rk3399_cru.c

714

PLIST(pll_src_cpll_gpll_npll_upll_24m_p)= { "cpll", "gpll", "npll", "upll", "xin24m" };

sys/dev/clk/rockchip/rk3399_cru.c

715

PLIST(pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };

sys/dev/clk/rockchip/rk3399_cru.c

716

PLIST(pll_src_vpll_cpll_gpll_gpll_p) = {"vpll", "cpll", "gpll", "gpll"};

sys/dev/clk/rockchip/rk3399_cru.c

717

PLIST(pll_src_vpll_cpll_gpll_npll_p) = {"vpll", "cpll", "gpll", "npll"};

sys/dev/clk/rockchip/rk3399_cru.c

719

PLIST(aclk_cci_p) = {"cpll_aclk_cci_src", "gpll_aclk_cci_src",

sys/dev/clk/rockchip/rk3399_cru.c

721

PLIST(cci_trace_p) = {"cpll_cci_trace","gpll_cci_trace"};

sys/dev/clk/rockchip/rk3399_cru.c

722

PLIST(cs_p)= {"cpll_cs", "gpll_cs", "npll_cs","npll_cs"};

sys/dev/clk/rockchip/rk3399_cru.c

723

PLIST(aclk_perihp_p)= {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };

sys/dev/clk/rockchip/rk3399_cru.c

724

PLIST(dclk_vop0_p) = {"dclk_vop0_div", "dclk_vop0_frac"};

sys/dev/clk/rockchip/rk3399_cru.c

725

PLIST(dclk_vop1_p)= {"dclk_vop1_div", "dclk_vop1_frac"};

sys/dev/clk/rockchip/rk3399_cru.c

727

PLIST(clk_cif_p) = {"clk_cifout_src", "xin24m"};

sys/dev/clk/rockchip/rk3399_cru.c

729

PLIST(pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m"};

sys/dev/clk/rockchip/rk3399_cru.c

730

PLIST(pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m"};

sys/dev/clk/rockchip/rk3399_cru.c

731

PLIST(pll_src_24m_32k_cpll_gpll_p)= {"xin24m", "xin32k", "cpll", "gpll"};

sys/dev/clk/rockchip/rk3399_cru.c

732

PLIST(pciecore_cru_phy_p) = {"clk_pcie_core_cru", "clk_pcie_core_phy"};

sys/dev/clk/rockchip/rk3399_cru.c

734

PLIST(aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src"};

sys/dev/clk/rockchip/rk3399_cru.c

736

PLIST(aclk_perilp0_p) = { "cpll_aclk_perilp0_src",

sys/dev/clk/rockchip/rk3399_cru.c

739

PLIST(fclk_cm0s_p) = { "cpll_fclk_cm0s_src",

sys/dev/clk/rockchip/rk3399_cru.c

742

PLIST(hclk_perilp1_p) = { "cpll_hclk_perilp1_src",

sys/dev/clk/rockchip/rk3399_cru.c

745

PLIST(clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };

sys/dev/clk/rockchip/rk3399_cru.c

746

PLIST(clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };

sys/dev/clk/rockchip/rk3399_cru.c

748

PLIST(usbphy_480m_p) = { "clk_usbphy0_480m_src",

sys/dev/clk/rockchip/rk3399_cru.c

750

PLIST(aclk_gmac_p) = { "cpll_aclk_gmac_src",

sys/dev/clk/rockchip/rk3399_cru.c

752

PLIST(rmii_p) = { "clk_gmac", "clkin_gmac" };

sys/dev/clk/rockchip/rk3399_cru.c

753

PLIST(spdif_p) = { "clk_spdif_div", "clk_spdif_frac",

sys/dev/clk/rockchip/rk3399_cru.c

755

PLIST(i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",

sys/dev/clk/rockchip/rk3399_cru.c

757

PLIST(i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",

sys/dev/clk/rockchip/rk3399_cru.c

759

PLIST(i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",

sys/dev/clk/rockchip/rk3399_cru.c

761

PLIST(i2sch_p) = {"clk_i2s0", "clk_i2s1", "clk_i2s2"};

sys/dev/clk/rockchip/rk3399_cru.c

762

PLIST(i2sout_p) = {"clk_i2sout_src", "xin12m"};

sys/dev/clk/rockchip/rk3399_cru.c

764

PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"};

sys/dev/clk/rockchip/rk3399_cru.c

765

PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"};

sys/dev/clk/rockchip/rk3399_cru.c

766

PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"};

sys/dev/clk/rockchip/rk3399_cru.c

767

PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"};

sys/dev/clk/rockchip/rk3399_pmucru.c

758

PLIST(xin24m_p) = {"xin24m"};

sys/dev/clk/rockchip/rk3399_pmucru.c

759

PLIST(xin24m_xin32k_p) = {"xin24m", "xin32k"};

sys/dev/clk/rockchip/rk3399_pmucru.c

760

PLIST(xin24m_ppll_p) = {"xin24m", "ppll"};

sys/dev/clk/rockchip/rk3399_pmucru.c

761

PLIST(uart4_p) = {"clk_uart4_c", "clk_uart4_frac", "xin24m"};

sys/dev/clk/rockchip/rk3399_pmucru.c

762

PLIST(wifi_p) = {"clk_wifi_c", "clk_wifi_frac"};

sys/dev/clk/rockchip/rk3568_cru.c

165

PLIST(mux_pll_p) = { "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

166

PLIST(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };

sys/dev/clk/rockchip/rk3568_cru.c

167

PLIST(mux_armclk_p) = { "apll", "gpll" };

sys/dev/clk/rockchip/rk3568_cru.c

168

PLIST(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac",

sys/dev/clk/rockchip/rk3568_cru.c

170

PLIST(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac",

sys/dev/clk/rockchip/rk3568_cru.c

172

PLIST(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac",

sys/dev/clk/rockchip/rk3568_cru.c

174

PLIST(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac",

sys/dev/clk/rockchip/rk3568_cru.c

176

PLIST(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac",

sys/dev/clk/rockchip/rk3568_cru.c

178

PLIST(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac",

sys/dev/clk/rockchip/rk3568_cru.c

180

PLIST(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac",

sys/dev/clk/rockchip/rk3568_cru.c

182

PLIST(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };

sys/dev/clk/rockchip/rk3568_cru.c

183

PLIST(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" };

sys/dev/clk/rockchip/rk3568_cru.c

184

PLIST(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

185

PLIST(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

186

PLIST(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

187

PLIST(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

188

PLIST(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

189

PLIST(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

190

PLIST(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

191

PLIST(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

192

PLIST(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

193

PLIST(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };

sys/dev/clk/rockchip/rk3568_cru.c

194

PLIST(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };

sys/dev/clk/rockchip/rk3568_cru.c

195

PLIST(npll_gpll_p) = { "npll", "gpll" };

sys/dev/clk/rockchip/rk3568_cru.c

196

PLIST(cpll_gpll_p) = { "cpll", "gpll" };

sys/dev/clk/rockchip/rk3568_cru.c

197

PLIST(gpll_cpll_p) = { "gpll", "cpll" };

sys/dev/clk/rockchip/rk3568_cru.c

198

PLIST(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };

sys/dev/clk/rockchip/rk3568_cru.c

199

PLIST(apll_gpll_npll_p) = { "apll", "gpll", "npll" };

sys/dev/clk/rockchip/rk3568_cru.c

200

PLIST(sclk_core_pre_p) = { "sclk_core_src", "npll" };

sys/dev/clk/rockchip/rk3568_cru.c

201

PLIST(gpll150_gpll100_gpll75_xin24m_p) = { "clk_gpll_div_150m", "clk_gpll_div_100m", "clk_gpll_div_75m",

sys/dev/clk/rockchip/rk3568_cru.c

203

PLIST(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" };

sys/dev/clk/rockchip/rk3568_cru.c

204

PLIST(clk_npu_pre_ndft_p) = { "clk_npu_src", "clk_npu_np5"};

sys/dev/clk/rockchip/rk3568_cru.c

205

PLIST(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" };

sys/dev/clk/rockchip/rk3568_cru.c

206

PLIST(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };

sys/dev/clk/rockchip/rk3568_cru.c

207

PLIST(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" };

sys/dev/clk/rockchip/rk3568_cru.c

208

PLIST(gpll200_gpll150_gpll100_xin24m_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m",

sys/dev/clk/rockchip/rk3568_cru.c

210

PLIST(gpll100_gpll75_gpll50_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m" };

sys/dev/clk/rockchip/rk3568_cru.c

211

PLIST(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" };

sys/dev/clk/rockchip/rk3568_cru.c

212

PLIST(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" };

sys/dev/clk/rockchip/rk3568_cru.c

213

PLIST(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" };

sys/dev/clk/rockchip/rk3568_cru.c

214

PLIST(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" };

sys/dev/clk/rockchip/rk3568_cru.c

215

PLIST(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" };

sys/dev/clk/rockchip/rk3568_cru.c

216

PLIST(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" };

sys/dev/clk/rockchip/rk3568_cru.c

217

PLIST(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" };

sys/dev/clk/rockchip/rk3568_cru.c

218

PLIST(mclk_pdm_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m", "clk_gpll_div_200m", "clk_gpll_div_100m" };

sys/dev/clk/rockchip/rk3568_cru.c

219

PLIST(clk_i2c_p) = { "clk_gpll_div_200m", "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" };

sys/dev/clk/rockchip/rk3568_cru.c

220

PLIST(gpll200_gpll150_gpll100_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_gpll_div_100m" };

sys/dev/clk/rockchip/rk3568_cru.c

221

PLIST(gpll300_gpll200_gpll100_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m", "clk_gpll_div_100m" };

sys/dev/clk/rockchip/rk3568_cru.c

222

PLIST(clk_nandc_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

223

PLIST(sclk_sfc_p) = { "xin24m", "clk_cpll_div_50m", "clk_gpll_div_75m", "clk_gpll_div_100m",

sys/dev/clk/rockchip/rk3568_cru.c

225

PLIST(gpll200_gpll150_cpll125_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_125m" };

sys/dev/clk/rockchip/rk3568_cru.c

226

PLIST(cclk_emmc_p) = { "xin24m", "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m",

sys/dev/clk/rockchip/rk3568_cru.c

228

PLIST(aclk_pipe_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_gpll_div_200m", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

229

PLIST(gpll200_cpll125_p) = { "clk_gpll_div_200m", "clk_cpll_div_125m" };

sys/dev/clk/rockchip/rk3568_cru.c

230

PLIST(gpll300_gpll200_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m",

sys/dev/clk/rockchip/rk3568_cru.c

232

PLIST(clk_sdmmc_p) = { "xin24m", "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_cpll_div_100m",

sys/dev/clk/rockchip/rk3568_cru.c

234

PLIST(cpll125_cpll50_cpll25_xin24m_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m",

sys/dev/clk/rockchip/rk3568_cru.c

236

PLIST(clk_gmac_ptp_p) = { "clk_cpll_div_62P5m", "clk_gpll_div_100m", "clk_cpll_div_50m", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

237

PLIST(cpll333_gpll300_gpll200_p) = { "clk_cpll_div_333m", "clk_gpll_div_300m", "clk_gpll_div_200m" };

sys/dev/clk/rockchip/rk3568_cru.c

238

PLIST(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };

sys/dev/clk/rockchip/rk3568_cru.c

239

PLIST(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" };

sys/dev/clk/rockchip/rk3568_cru.c

240

PLIST(gpll300_cpll250_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m",

sys/dev/clk/rockchip/rk3568_cru.c

242

PLIST(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" };

sys/dev/clk/rockchip/rk3568_cru.c

243

PLIST(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" };

sys/dev/clk/rockchip/rk3568_cru.c

244

PLIST(gpll400_cpll333_gpll200_p) = { "clk_gpll_div_400m", "clk_cpll_div_333m", "clk_gpll_div_200m" };

sys/dev/clk/rockchip/rk3568_cru.c

245

PLIST(gpll100_gpll75_cpll50_xin24m_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m",

sys/dev/clk/rockchip/rk3568_cru.c

247

PLIST(xin24m_gpll100_cpll100_p) = { "xin24m", "clk_gpll_div_100m", "clk_cpll_div_100m" };

sys/dev/clk/rockchip/rk3568_cru.c

248

PLIST(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" };

sys/dev/clk/rockchip/rk3568_cru.c

249

PLIST(gpll100_xin24m_cpll100_p) = { "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" };

sys/dev/clk/rockchip/rk3568_cru.c

250

PLIST(gpll200_xin24m_cpll100_p) = { "clk_gpll_div_200m", "xin24m", "clk_cpll_div_100m" };

sys/dev/clk/rockchip/rk3568_cru.c

251

PLIST(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };

sys/dev/clk/rockchip/rk3568_cru.c

252

PLIST(cpll500_gpll400_gpll300_xin24m_p) = { "clk_cpll_div_500m", "clk_gpll_div_400m",

sys/dev/clk/rockchip/rk3568_cru.c

254

PLIST(gpll400_gpll300_gpll200_xin24m_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m",

sys/dev/clk/rockchip/rk3568_cru.c

256

PLIST(xin24m_cpll100_p) = { "xin24m", "clk_cpll_div_100m" };

sys/dev/clk/rockchip/rk3568_cru.c

257

PLIST(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" };

sys/dev/clk/rockchip/rk3568_cru.c

258

PLIST(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0",

sys/dev/clk/rockchip/rk3568_cru.c

260

PLIST(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };

sys/dev/clk/rockchip/rk3568_cru.c

261

PLIST(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed",

sys/dev/clk/rockchip/rk3568_cru.c

263

PLIST(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" };

sys/dev/clk/rockchip/rk3568_cru.c

264

PLIST(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1",

sys/dev/clk/rockchip/rk3568_cru.c

266

PLIST(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };

sys/dev/clk/rockchip/rk3568_cru.c

267

PLIST(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed",

sys/dev/clk/rockchip/rk3568_cru.c

269

PLIST(clk_mac_2top_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m", "ppll" };

sys/dev/clk/rockchip/rk3568_cru.c

270

PLIST(aclk_rkvdec_pre_p) = { "gpll", "cpll" };

sys/dev/clk/rockchip/rk3568_cru.c

271

PLIST(clk_rkvdec_core_p) = { "gpll", "cpll", "npll", "vpll" };

sys/dev/clk/rockchip/rk3568_pmucru.c

74

PLIST(mux_pll_p) = { "xin24m" };

sys/dev/clk/rockchip/rk3568_pmucru.c

75

PLIST(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };

sys/dev/clk/rockchip/rk3568_pmucru.c

76

PLIST(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };

sys/dev/clk/rockchip/rk3568_pmucru.c

77

PLIST(sclk_uart0_div_p) = { "ppll", "usb480m", "cpll", "gpll" };

sys/dev/clk/rockchip/rk3568_pmucru.c

78

PLIST(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_osc0_div32k" };

sys/dev/clk/rockchip/rk3568_pmucru.c

79

PLIST(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" };

sys/dev/clk/rockchip/rk3568_pmucru.c

80

PLIST(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" };

sys/dev/clk/rockchip/rk3568_pmucru.c

81

PLIST(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" };

sys/dev/clk/rockchip/rk3568_pmucru.c

82

PLIST(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" };

sys/dev/clk/rockchip/rk3568_pmucru.c

83

PLIST(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };

sys/dev/clk/rockchip/rk3568_pmucru.c

84

PLIST(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" };

sys/dev/clk/rockchip/rk3568_pmucru.c

85

PLIST(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" };

sys/dev/clk/rockchip/rk3568_pmucru.c

86

PLIST(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" };

sys/dev/clk/rockchip/rk3568_pmucru.c

87

PLIST(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" };

sys/dev/clk/rockchip/rk3568_pmucru.c

88

PLIST(clk_pdpmu_p) = { "ppll", "gpll" };

sys/dev/clk/rockchip/rk3568_pmucru.c

89

PLIST(clk_pwm0_p) = { "xin24m", "clk_pdpmu" };