PCIR_CACHELNSZ
cz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
pci_write_config(dev, PCIR_CACHELNSZ,
pci_write_config(dev, PCIR_CACHELNSZ, 0x08, 1);
cache_line = ocache_line = pci_read_config(self, PCIR_CACHELNSZ, 1);
pci_write_config(self, PCIR_CACHELNSZ, cache_line, 1);
pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
PCIR_CACHELNSZ) {
#ifndef PCIR_CACHELNSZ
data = pci_read_config(dev, PCIR_CACHELNSZ, 1);
pci_write_config(dev, PCIR_CACHELNSZ, data, 1);
pci_read_config(mpt->dev, PCIR_CACHELNSZ, 2);
MPT_CHECK(LatencyTimer_LineSize, PCIR_CACHELNSZ, 2);
pci_write_config(mpt->dev, PCIR_CACHELNSZ,
val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1);