PCIER_LINK_CTL
#define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
#define PCI_EXP_LNKCTL PCIER_LINK_CTL
PCIER_LINK_CTL);
CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL);
cfg = pcie_read_config(sc->pci_dev, PCIER_LINK_CTL, 2);
pcie_write_config(sc->pci_dev, PCIER_LINK_CTL, cfg, 2);
lcreg = pcie_read_config(sc->pci_dev, PCIER_LINK_CTL, 2);
pcie_write_config(sc->pci_dev, PCIER_LINK_CTL, lcreg, 2);
#define PCI_EXP_LNKCTL PCIER_LINK_CTL
#define PCI_EXP_LNKCTL PCIER_LINK_CTL
lctl = v + PCIER_LINK_CTL;
reg = base + PCIER_LINK_CTL;
lctl = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_LINK_CTL,
reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);
reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);
lctl = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_LINK_CTL,
WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2);
pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
PCIER_LINK_CTL, 2);
PCIER_LINK_CTL, ctl, 2);
sc->rl_expcap + PCIER_LINK_CTL, 2);
sc->rl_expcap + PCIER_LINK_CTL, ctl, 2);
ecap + PCIER_LINK_CTL, 2);
ecap + PCIER_LINK_CTL, lctl, 2);
pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL + 1, 1, 1);
val = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, 1);
pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, val & 0xfc, 1);
lcsr = pci_read_config(dev, cap_off + PCIER_LINK_CTL, 4);
pci_write_config(dev, cap_off + PCIER_LINK_CTL, lcsr, 4);
linkctl = pci_read_config(dev, capmem + PCIER_LINK_CTL, 2);
pci_write_config(dev, capmem + PCIER_LINK_CTL, (linkctl |
reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 1);
reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 1);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2);