PCLK_UART0
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 6, 8),
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 16, 11),
GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 22, 0),
GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 1, 2),