PCIR_COMMAND
cmd1 = cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
pci_write_config(dev, PCIR_COMMAND, cmd1, 2);
cmd = pci_read_config(ppt->dev, PCIR_COMMAND, 2);
pci_write_config(ppt->dev, PCIR_COMMAND, cmd, 2);
cmd = pci_read_config(ppt->dev, PCIR_COMMAND, 2);
pci_write_config(ppt->dev, PCIR_COMMAND, cmd, 2);
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
func, PCIR_COMMAND, 1);
PCIR_COMMAND, command, 1);
PCIR_COMMAND, command, 1);
PRIV_CFG_WR2(sc, PCIR_COMMAND, PCIM_CMD_MEMEN |
#define PCI_COMMAND PCIR_COMMAND
return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) &
if (!(pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_BUSMASTEREN)) {
command = pci_read_config(sc->aac_dev, PCIR_COMMAND, 2);
cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
(void) pci_read_config(dev, PCIR_COMMAND, 4);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN |
pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
#define PCI_COMMAND_REGISTER PCIR_COMMAND
sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
cmd = pci_read_config(self, PCIR_COMMAND, 2);
pci_write_config(self, PCIR_COMMAND, cmd, 2);
val = pci_read_config(dev, PCIR_COMMAND, 2);
if (where + size <= PCIR_COMMAND) {
if (where >= PCIR_COMMAND && where + size <= CFG_PAGE_SIZE) {
sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
#ifndef PCIR_COMMAND
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
#define PCI_COMMAND_REGISTER PCIR_COMMAND
#define PCI_COMMAND_REGISTER PCIR_COMMAND
pci_write_config(oct->device, PCIR_COMMAND, PCIM_CMD_INTxDIS, 2);
val = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, val, 2);
mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2);
MPT_CHECK(Command, PCIR_COMMAND, 2);
pci_write_config(mpt->dev, PCIR_COMMAND, mpt->pci_cfg.Command, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
reg = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, reg, 2);
PNTX_WRITE(sc, PCIR_COMMAND, PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
val = pci_read_config(ocs->dev, PCIR_COMMAND, 2);
pci_write_config(ocs->dev, PCIR_COMMAND, val, 2);
command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND,
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
cmd = pci_read_config(child, PCIR_COMMAND, 2);
pci_write_config(child, PCIR_COMMAND,
pci_write_config(child, PCIR_COMMAND, cmd, 2);
pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
cfg->cmdreg = REG(PCIR_COMMAND, 2);
DBI_WR2(sc, PCIR_COMMAND,
pci_write_config(dev, PCIR_COMMAND, pci_get_cmdreg(dev), 2);
config = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, config | PCIM_CMD_INTxDIS, 2);
command = pci_read_config(softs->os_specific.pqi_dev, PCIR_COMMAND, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
command = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, command, 2);
(pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_BUSMASTEREN)
(pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_BUSMASTEREN)
d = pci_read_config(dev, PCIR_COMMAND, 2);
cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN);
cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
new = pci_get_cfgdata16(pi, PCIR_COMMAND);
cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
} else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) {
cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND);
pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit);
if ((error = set_pcir_handler(sc, PCIR_COMMAND, 0x04, NULL, NULL)) != 0)
if (coff == PCIR_COMMAND) {
*rv = (st << 16) | pci_get_cfgdata16(pi, PCIR_COMMAND);
if (coff == PCIR_COMMAND) {
cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);
pci_set_cfgdata16(pi, PCIR_COMMAND, val & 0xffff);
cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
pci_set_cfgdata16(pi, PCIR_COMMAND, cmd);