PCIER_DEVICE_CTL
#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL);
sc->bge_expcap + PCIER_DEVICE_CTL, 2);
pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
devctl = bxe_pcie_capability_read(sc, PCIER_DEVICE_CTL, 2);
#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
pci_write_config(oct->device, exppos + PCIER_DEVICE_CTL, PCIEM_CTL_INITIATE_FLR, 2);
val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) &
mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) &
pcie_adjust_config(root, PCIER_DEVICE_CTL,
pcie_adjust_config(dev, PCIER_DEVICE_CTL,
PCIER_DEVICE_CTL, 2);
PCIER_DEVICE_CTL, r, 2);
WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl |
PCIER_DEVICE_CTL, 2),
cap_reg += PCIER_DEVICE_CTL; /* Offset for Device Control Register. */
devctl = pci_read_config(dev, capmem + PCIER_DEVICE_CTL, 2);
pci_write_config(dev, capmem + PCIER_DEVICE_CTL, (devctl |
sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2);