OCE_READ_REG32
reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);
sliport_err1 = OCE_READ_REG32(sc, db, SLIPORT_ERROR1_OFFSET);
sliport_err2 = OCE_READ_REG32(sc, db, SLIPORT_ERROR2_OFFSET);
ue_low = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW);
ue_high = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HIGH);
ue_low_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW_MASK);
ue_high_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HI_MASK);
mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);