NFE_WRITE
NFE_WRITE(sc, NFE_MISC1, val);
NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
NFE_WRITE(sc, NFE_PHY_DATA, val);
NFE_WRITE(sc, NFE_PHY_CTL, ctl);
NFE_WRITE(sc, sc->nfe_irq_status, r);
NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED);
NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs);
NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs);
NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs);
NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs);
NFE_WRITE(sc, sc->nfe_irq_status, r);
NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
NFE_WRITE(sc, NFE_MULTIADDR_HI, ctx.addr[3] << 24 | ctx.addr[2] << 16 |
NFE_WRITE(sc, NFE_MULTIADDR_LO,
NFE_WRITE(sc, NFE_MULTIMASK_HI, ctx.mask[3] << 24 | ctx.mask[2] << 16 |
NFE_WRITE(sc, NFE_MULTIMASK_LO,
NFE_WRITE(sc, NFE_RXFILTER, filter);
NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
NFE_WRITE(sc, NFE_TX_UNK, val);
NFE_WRITE(sc, NFE_STATUS, 0);
NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE);
NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
NFE_WRITE(sc, NFE_VTAG_CTL, 0);
NFE_WRITE(sc, NFE_SETUP_R6, 0);
NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
NFE_WRITE(sc, NFE_RX_RING_ADDR_LO,
NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
NFE_WRITE(sc, NFE_RX_RING_ADDR_LO,
NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr));
NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr));
NFE_WRITE(sc, NFE_RING_SIZE,
NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize);
NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP);
NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID);
NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT);
NFE_WRITE(sc, NFE_IMTIMER, 970);
NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100);
NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
NFE_WRITE(sc, NFE_WOL_CTL, 0);
NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
NFE_WRITE(sc, NFE_TX_CTL, 0);
NFE_WRITE(sc, NFE_RX_CTL, 0);
NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]);
NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 |
NFE_WRITE(sc, NFE_WOL_CTL, wolctl);
NFE_WRITE(sc, NFE_PWR2_CTL,
NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 0);
NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 0);
NFE_WRITE(sc, NFE_RX_CTL, NFE_READ(sc, NFE_RX_CTL) |
NFE_WRITE(sc, NFE_MSIX_MAP0, 0);
NFE_WRITE(sc, NFE_MSIX_MAP1, 0);
NFE_WRITE(sc, NFE_MSI_MAP0, 0);
NFE_WRITE(sc, NFE_MSI_MAP1, 0);
NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2);
NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC);
NFE_WRITE(sc, NFE_MAC_RESET, 0);
NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2);
NFE_WRITE(sc, NFE_PWR2_CTL, pwr);
NFE_WRITE(sc, NFE_TX_CTL, txctl);
NFE_WRITE(sc, NFE_RX_CTL, rxctl);
NFE_WRITE(sc, NFE_SETUP_R1, val);
NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
NFE_WRITE(sc, NFE_PHY_IFACE, phy);
NFE_WRITE(sc, NFE_MISC1, misc);
NFE_WRITE(sc, NFE_LINKSPEED, link);
NFE_WRITE(sc, NFE_RXFILTER, val);
NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
NFE_WRITE(sc, NFE_MISC1, val);
NFE_WRITE(sc, NFE_RXFILTER, val);
NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,