MV_U32
MV_U32 offset, void *value, int size, int reading);
MV_U16 responseFlags, MV_U32 timeStamp,
MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2);
MV_U32 timeStamp,
pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0);
pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress;
MV_U32 udmaMode,pioMode;
MV_U32 param1, MV_U32 param2)
mvMicroSecondsDelay(MV_U32 msecs)
MV_REG_WRITE_BYTE(MV_BUS_ADDR_T base, MV_U32 offset, MV_U8 val)
MV_REG_WRITE_WORD(MV_BUS_ADDR_T base, MV_U32 offset, MV_U16 val)
MV_REG_WRITE_DWORD(MV_BUS_ADDR_T base, MV_U32 offset, MV_U32 val)
MV_REG_READ_BYTE(MV_BUS_ADDR_T base, MV_U32 offset)
MV_REG_READ_WORD(MV_BUS_ADDR_T base, MV_U32 offset)
MV_U32 HPTLIBAPI
MV_REG_READ_DWORD(MV_BUS_ADDR_T base, MV_U32 offset)
extern void HPTLIBAPI MV_REG_WRITE_DWORD(MV_BUS_ADDR_T base, MV_U32 offset, MV_U32 val);
extern MV_U8 HPTLIBAPI MV_REG_READ_BYTE(MV_BUS_ADDR_T base, MV_U32 offset);
extern MV_U16 HPTLIBAPI MV_REG_READ_WORD(MV_BUS_ADDR_T base, MV_U32 offset);
extern MV_U32 HPTLIBAPI MV_REG_READ_DWORD(MV_BUS_ADDR_T base, MV_U32 offset);
void HPTLIBAPI mvMicroSecondsDelay(MV_U32);
typedef MV_U32 *MV_U32_PTR;
extern void HPTLIBAPI MV_REG_WRITE_BYTE(MV_BUS_ADDR_T base, MV_U32 offset, MV_U8 val);
extern void HPTLIBAPI MV_REG_WRITE_WORD(MV_BUS_ADDR_T base, MV_U32 offset, MV_U16 val);
MV_U32,
MV_U32 lowLBAAddress;
MV_U32 prdLowAddr;
MV_U32 prdHighAddr;
MV_U32 count;
MV_U32 requestQueuePciHiAddress;
MV_U32 requestQueuePciLowAddress;
MV_U32 responseQueuePciHiAddress;
MV_U32 responseQueuePciLowAddress;
MV_U32 eDmaRegsOffset;
MV_U32 freeIDsStack[CHANNEL_QUEUE_LENGTH];
MV_U32 freeIDsNum;
MV_U32 reqInPtr;
MV_U32 rspOutPtr;
MV_U32 adapterId;
MV_U32 intCoalThre[MV_SATA_UNITS_NUM];
MV_U32 intTimeThre[MV_SATA_UNITS_NUM];
MV_U32, MV_U32);
MV_U32 pciCommand;
MV_U32 pciSerrMask;
MV_U32 pciInterruptMask;
MV_U32 mainMask;
MV_U32 pciDLLStatusAndControlRegister;
MV_U32 pciCommandRegister;
MV_U32 pciModeRegister;
MV_U32 pciSERRMaskRegister;
MV_U32 intCoalThre[MV_SATA_UNITS_NUM];
MV_U32 intTimeThre[MV_SATA_UNITS_NUM];
MV_U32 R00StatusBridgePortRegister[MV_SATA_CHANNELS_NUM];
MV_U32 EdmaConfigurationRegister;
MV_U32 EdmaRequestQueueBaseAddressHighRegister;
MV_U32 EdmaRequestQueueInPointerRegister;
MV_U32 EdmaRequestQueueOutPointerRegister;
MV_U32 EdmaResponseQueueBaseAddressHighRegister;
MV_U32 EdmaResponseQueueInPointerRegister;
MV_U32 EdmaResponseQueueOutPointerRegister;
MV_U32 EdmaCommandRegister;
MV_U32 PHYModeRegister;
volatile MV_U32 lowBaseAddr;
volatile MV_U32 highBaseAddr;
volatile MV_U32 reserved;
MV_U32 HPTLIBAPI mvSataReadReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset);
MV_VOID HPTLIBAPI mvSataWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset,
MV_U32 regValue);
MV_U32 intCoalThre, MV_U32 intTimeThre);
MV_U32, MV_U32);
MV_U16 FAR *bufPtr, MV_U32 count,
MV_U8 good, MV_U8 bad, MV_U32 loops, MV_U32 delay);