sys/arm/mv/armadaxp/armadaxp.c

56

#define ARMADAXP_L2_BASE (MV_BASE + 0x8000)

sys/arm/mv/armadaxp/armadaxp_mp.c

116

pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT;

sys/arm/mv/armadaxp/armadaxp_mp.c

166

bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0);

sys/arm/mv/armadaxp/armadaxp_mp.c

53

#define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700)

sys/arm/mv/armadaxp/armadaxp_mp.c

59

#define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x)))

sys/arm/mv/armadaxp/armadaxp_mp.c

62

#define MP (MV_BASE + 0x20800)

sys/arm/mv/mv_armv7_machdep.c

299

fdt_immr_va = MV_BASE;

sys/arm/mv/mvreg.h

312

#define MV_SCU_BASE (MV_BASE + 0xc000)

sys/arm/mv/mvreg.h

323

#define MV_PMSU_BASE (MV_BASE + 0x22000)

sys/arm/mv/mvreg.h

330

#define MV_CPU_RESET_BASE (MV_BASE + 0x20800)

sys/arm/mv/mvreg.h

335

#define MV_MBUS_CTRL_BASE (MV_BASE + 0x20420)

sys/arm/mv/mvwin.h

105

#define MV_PCI_BASE (MV_BASE + 0x30000)

sys/arm/mv/mvwin.h

108

#define MV_PCIE_BASE_ARMADA38X (MV_BASE + 0x80000)

sys/arm/mv/mvwin.h

109

#define MV_PCIE_BASE (MV_BASE + 0x40000)

sys/arm/mv/mvwin.h

111

#define MV_SDIO_BASE (MV_BASE + 0x90000)

sys/arm/mv/mvwin.h

93

#define MV_DDR_CADR_BASE_ARMV7 (MV_BASE + 0x20180)

sys/arm/mv/mvwin.h

94

#define MV_DDR_CADR_BASE (MV_BASE + 0x1500)

sys/arm/mv/mvwin.h

95

#define MV_MPP_BASE (MV_BASE + 0x10000)

sys/arm/mv/mvwin.h

97

#define MV_MISC_BASE (MV_BASE + 0x18200)

sys/arm/mv/mvwin.h

98

#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)