sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1015

case MLX5_PARAM_OFFSET(rx_queue_size):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1041

case MLX5_PARAM_OFFSET(channels_rsss):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1059

case MLX5_PARAM_OFFSET(channels):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1079

case MLX5_PARAM_OFFSET(rx_coalesce_mode):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1099

case MLX5_PARAM_OFFSET(tx_coalesce_mode):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1119

case MLX5_PARAM_OFFSET(hw_lro):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1147

case MLX5_PARAM_OFFSET(cqe_zipping):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1166

case MLX5_PARAM_OFFSET(tx_completion_fact):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1179

case MLX5_PARAM_OFFSET(modify_tx_dma):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1192

case MLX5_PARAM_OFFSET(modify_rx_dma):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1205

case MLX5_PARAM_OFFSET(diag_pci_enable):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1214

case MLX5_PARAM_OFFSET(diag_general_enable):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1223

case MLX5_PARAM_OFFSET(mc_local_lb):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1241

case MLX5_PARAM_OFFSET(uc_local_lb):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1259

case MLX5_PARAM_OFFSET(irq_cpu_base):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1260

case MLX5_PARAM_OFFSET(irq_cpu_stride):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

917

switch (MLX5_PARAM_OFFSET(arg[arg2])) {

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

918

case MLX5_PARAM_OFFSET(rx_coalesce_usecs):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

935

case MLX5_PARAM_OFFSET(rx_coalesce_pkts):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

952

case MLX5_PARAM_OFFSET(tx_coalesce_usecs):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

969

case MLX5_PARAM_OFFSET(tx_coalesce_pkts):

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

986

case MLX5_PARAM_OFFSET(tx_queue_size):