MEMAC_COMMAND_CONFIG
reg = bus_read_4(sc->sc_base.sc_mem, MEMAC_COMMAND_CONFIG);
bus_write_4(sc->sc_base.sc_mem, MEMAC_COMMAND_CONFIG, reg);
while (bus_read_4(sc->sc_base.sc_mem, MEMAC_COMMAND_CONFIG) & COMMAND_CONFIG_SWR)
bus_write_4(sc->sc_base.sc_mem, MEMAC_COMMAND_CONFIG,
reg = bus_read_4(sc->sc_base.sc_mem, MEMAC_COMMAND_CONFIG);
bus_write_4(sc->sc_base.sc_mem, MEMAC_COMMAND_CONFIG,
reg = bus_read_4(regs, MEMAC_COMMAND_CONFIG);
bus_write_4(regs, MEMAC_COMMAND_CONFIG, reg);
bus_write_4(regs, MEMAC_COMMAND_CONFIG, reg);
bus_write_4(regs, MEMAC_COMMAND_CONFIG, reg & ~COMMAND_CONFIG_TX_EN);
uint32_t reg = bus_read_4(sc->sc_base.sc_mem, MEMAC_COMMAND_CONFIG);
bus_write_4(sc->sc_base.sc_mem, MEMAC_COMMAND_CONFIG, reg);