sys/dev/mlx5/mlx5_fpga/mlx5fpga_cmd.c

95

unsigned int cap_size = MLX5_CAP_FPGA(dev, sandbox_extended_caps_len);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

167

fpga_id = MLX5_CAP_FPGA(fdev->mdev, fpga_id);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

228

fpga_id = MLX5_CAP_FPGA(fdev->mdev, fpga_id);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

237

MLX5_CAP_FPGA(fdev->mdev, image_version),

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

238

MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id),

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

239

MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id),

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

240

MLX5_CAP_FPGA(fdev->mdev, sandbox_product_version));

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

242

max_num_qps = MLX5_CAP_FPGA(mdev, shell_caps.max_num_qps);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

286

vid = MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

287

pid = MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

371

fpga_id = MLX5_CAP_FPGA(mdev, fpga_id);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

412

max_num_qps = MLX5_CAP_FPGA(mdev, shell_caps.max_num_qps);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

531

vid = MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_core.c

532

pid = MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id);

sys/dev/mlx5/mlx5_fpga/mlx5fpga_ipsec.c

83

if (MLX5_CAP_FPGA(mdev, ieee_vendor_id) !=

sys/dev/mlx5/mlx5_fpga/mlx5fpga_ipsec.c

87

if (MLX5_CAP_FPGA(mdev, sandbox_product_id) !=

sys/dev/mlx5/mlx5_fpga/mlx5fpga_sdk.c

267

return (u64)MLX5_CAP_FPGA(fdev->mdev, fpga_ddr_size) << 10;