sys/dev/mlx5/mlx5_core/mlx5_vport.c

231

switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {

sys/dev/mlx5/mlx5_en/mlx5_en_ethtool.c

1126

MLX5_CAP_ETH(priv->mdev, lro_cap)) {

sys/dev/mlx5/mlx5_en/mlx5_en_iq.c

270

if (MLX5_CAP_ETH(iq->priv->mdev, reg_umr_sq))

sys/dev/mlx5/mlx5_en/mlx5_en_main.c

1627

if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))

sys/dev/mlx5/mlx5_en/mlx5_en_main.c

2925

(MLX5_CAP_ETH(priv->mdev, lro_max_msg_sz_mode) == 0 ? 1 : 0));

sys/dev/mlx5/mlx5_en/mlx5_en_main.c

2936

MLX5_CAP_ETH(priv->mdev, lro_timer_supported_periods[2]));

sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c

714

if (MLX5_CAP_ETH(mdev, csum_cap))

sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c

718

max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);

sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c

754

MLX5_CAP_ETH(dev->mdev, scatter_fcs))

sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c

1661

!MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {