MLX4_MAX_PORTS
DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
int vl_cap[MLX4_MAX_PORTS + 1];
int ib_mtu_cap[MLX4_MAX_PORTS + 1];
__be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
u64 def_mac[MLX4_MAX_PORTS + 1];
int eth_mtu_cap[MLX4_MAX_PORTS + 1];
int gid_table_len[MLX4_MAX_PORTS + 1];
int pkey_table_len[MLX4_MAX_PORTS + 1];
int trans_type[MLX4_MAX_PORTS + 1];
int vendor_oui[MLX4_MAX_PORTS + 1];
int wavelength[MLX4_MAX_PORTS + 1];
u64 trans_code[MLX4_MAX_PORTS + 1];
u8 port_width_cap[MLX4_MAX_PORTS + 1];
enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
u8 supported_type[MLX4_MAX_PORTS + 1];
u8 suggested_type[MLX4_MAX_PORTS + 1];
u8 default_sense[MLX4_MAX_PORTS + 1];
u32 port_mask[MLX4_MAX_PORTS + 1];
enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
u64 phys_port_id[MLX4_MAX_PORTS + 1];
u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
u8 phv_bit[MLX4_MAX_PORTS + 1];
int nvfs[MLX4_MAX_PORTS + 1];
enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1];
u16 mtu[MLX4_MAX_PORTS + 1];
__be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
u8 enable_smi[MLX4_MAX_PORTS + 1];
struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
u8 smi_enabled[MLX4_MAX_PORTS + 1];
int res_port_rsvd[MLX4_MAX_PORTS];
int res_port_free[MLX4_MAX_PORTS];
struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
int init_port_ref[MLX4_MAX_PORTS + 1];
u16 max_mtu[MLX4_MAX_PORTS + 1];
int disable_mcast_ref[MLX4_MAX_PORTS + 1];
struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1];
u8 do_sense_port[MLX4_MAX_PORTS + 1];
u8 sense_allowed[MLX4_MAX_PORTS + 1];
int def_counter[MLX4_MAX_PORTS];
struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
for (port = 1; port <= MLX4_MAX_PORTS; port++) {
for (port = 1; port <= MLX4_MAX_PORTS; port++)
for (port = 1; port <= MLX4_MAX_PORTS; port++)
bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
port < 1 || port > MLX4_MAX_PORTS)
port < 1 || port > MLX4_MAX_PORTS)
port < 1 || port > MLX4_MAX_PORTS ||
enum mlx4_port_type types[MLX4_MAX_PORTS];
enum mlx4_port_type new_types[MLX4_MAX_PORTS];
if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
(port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
if (dev_cap->num_ports > MLX4_MAX_PORTS) {
dev_cap->num_ports, MLX4_MAX_PORTS);
for (i = 0; i < MLX4_MAX_PORTS; i++) {
int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
if (dev->caps.num_ports > MLX4_MAX_PORTS) {
dev->caps.num_ports, MLX4_MAX_PORTS);
8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k;
(MLX4_PF_COUNTERS_PER_PORT * MLX4_MAX_PORTS))
/ MLX4_MAX_PORTS;
res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
for (j = 0; j < MLX4_MAX_PORTS; j++)
for (j = 0; j < MLX4_MAX_PORTS; j++)
MLX4_MAX_PORTS;
MLX4_MAX_PORTS;
enum mlx4_port_type stype[MLX4_MAX_PORTS];
struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
if_t pndev[MLX4_MAX_PORTS + 1];
u8 mac_removed[MLX4_MAX_PORTS + 1];
for (i = 1; i <= MLX4_MAX_PORTS; i++) {
mdev->pdev->dev.bsddev) * MLX4_MAX_PORTS) + port - 1);
struct mlx4_sriov_alias_guid_port_rec_det ports_guid[MLX4_MAX_PORTS];
struct mlx4_ib_demux_ctx demux[MLX4_MAX_PORTS];
struct mlx4_ib_demux_pv_ctx *sqps[MLX4_MAX_PORTS];
if_t netdevs[MLX4_MAX_PORTS];
atomic64_t mac[MLX4_MAX_PORTS];
struct mlx4_port_gid_table gids[MLX4_MAX_PORTS];
u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
u16 phys_pkey_cache[MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
struct ib_mad_agent *send_agent[MLX4_MAX_PORTS][2];
struct ib_ah *sm_ah[MLX4_MAX_PORTS];
atomic64_t sl2vl[MLX4_MAX_PORTS];
struct mlx4_ib_counters counters_table[MLX4_MAX_PORTS];
struct mlx4_ib_iov_port iov_ports[MLX4_MAX_PORTS];
struct mlx4_ib_qp *qp1_proxy[MLX4_MAX_PORTS];
struct mutex qp1_proxy_lock[MLX4_MAX_PORTS];
if (port_num > MLX4_MAX_PORTS)
for (i = 0; i < MLX4_MAX_PORTS; ++i) {
if (port_num > MLX4_MAX_PORTS)
if (port_num > MLX4_MAX_PORTS)