crypto/openssl/crypto/evp/legacy_md4.c

20

IMPLEMENT_LEGACY_EVP_MD_METH(md4, MD4)

crypto/openssl/include/openssl/md4.h

53

OSSL_DEPRECATEDIN_3_0 unsigned char *MD4(const unsigned char *d, size_t n,

sys/arm/nvidia/tegra124/tegra124_clk_per.c

554

MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

661

MD4(sc, sc->base_reg, sc->div_mask,

sys/arm/nvidia/tegra124/tegra124_clk_per.c

765

MD4(sc, base_reg, mask, enable ? mask : 0);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

730

MD4(sc, sc->iddq_reg, sc->iddq_mask, 0);

sys/arm64/freescale/imx/clk/imx_clk_gate.c

85

rv = MD4(clk, sc->offset, sc->mask << sc->shift,

sys/arm64/freescale/imx/clk/imx_clk_mux.c

103

rv = MD4(clk, sc->offset, sc->mask << sc->shift,

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

667

MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

775

MD4(sc, sc->base_reg, sc->div_mask,

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

879

MD4(sc, base_reg, mask, enable ? mask : 0);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

928

MD4(sc, sc->iddq_reg, sc->iddq_mask, 0);

sys/dev/clk/clk_div.c

222

rv = MD4(clk, sc->offset,

sys/dev/clk/clk_gate.c

89

rv = MD4(clk, sc->offset, sc->mask << sc->shift,

sys/dev/clk/clk_mux.c

100

rv = MD4(clk, sc->offset, sc->mask << sc->shift,

sys/dev/clk/rockchip/rk_clk_gate.c

100

rv = MD4(clk, sc->offset, sc->mask << sc->shift,

sys/dev/clk/rockchip/rk_clk_mux.c

151

rv = MD4(clk, sc->offset, sc->mask << sc->shift,

sys/dev/hwpmc/pmu_dmc620.c

73

#define CD2MD4(sc, u, r, c, s) MD4((sc), DMC620_CLKDIV2_REG((u), (r)), (c), (s))

sys/dev/hwpmc/pmu_dmc620.c

74

#define CMD4(sc, u, r, c, s) MD4((sc), DMC620_CLK_REG((u), (r)), (c), (s))