sys/arm64/arm64/pmap.c

2921

l1 = &l1[ptepindex & Ln_ADDR_MASK];

sys/arm64/arm64/pmap.c

2945

l1 = &l1[l1index & Ln_ADDR_MASK];

sys/arm64/arm64/pmap.c

2948

l1 = &l1[l1index & Ln_ADDR_MASK];

sys/arm64/arm64/pmap.c

2965

l2 = &l2[ptepindex & Ln_ADDR_MASK];

sys/arm64/include/pte.h

254

#define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)

sys/arm64/include/pte.h

255

#define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)

sys/arm64/include/pte.h

256

#define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)

sys/arm64/iommu/iommu_pmap.c

499

l1 = &l1[ptepindex & Ln_ADDR_MASK];

sys/arm64/iommu/iommu_pmap.c

520

l1 = &l1[l1index & Ln_ADDR_MASK];

sys/arm64/iommu/iommu_pmap.c

523

l1 = &l1[l1index & Ln_ADDR_MASK];

sys/arm64/iommu/iommu_pmap.c

540

l2 = &l2[ptepindex & Ln_ADDR_MASK];

sys/riscv/riscv/pmap.c

1760

l1 = &l1[ptepindex & Ln_ADDR_MASK];

sys/riscv/riscv/pmap.c

1794

l1 = &l1[l1index & Ln_ADDR_MASK];

sys/riscv/riscv/pmap.c

1798

l1 = &l1[l1index & Ln_ADDR_MASK];

sys/riscv/riscv/pmap.c

1813

l2 = &l2[ptepindex & Ln_ADDR_MASK];

sys/riscv/riscv/pmap.c

370

#define pmap_l0_index(va) (((va) >> L0_SHIFT) & Ln_ADDR_MASK)

sys/riscv/riscv/pmap.c

371

#define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)

sys/riscv/riscv/pmap.c

372

#define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)

sys/riscv/riscv/pmap.c

373

#define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)