sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

102

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

126

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

127

(OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA)

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

140

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

141

OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));

sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c

99

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

275

uint32_t val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

282

uint32_t val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

288

OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

323

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

325

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

508

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

511

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

34

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

76

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);

sys/dev/ath/ath_hal/ar5210/ar5210_power.c

88

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SV);

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

127

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4));

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

314

val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

317

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

324

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

331

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5210/ar5210_reset.c

337

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

108

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

111

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

132

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

133

OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

145

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c

146

OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

510

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

513

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

65

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

77

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5211/ar5211_power.c

90

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2093

val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2096

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2102

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

2109

OS_REG_WRITE(ah, AR_STA_ID1, val

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

241

macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

377

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

132

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

135

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

155

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

156

OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

168

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c

169

OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

319

reg = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

321

OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

323

OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

535

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c

538

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

110

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

84

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5212/ar5212_power.c

97

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

242

macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

426

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

806

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

810

OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

815

OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC

sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

821

OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

192

macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &

sys/dev/ath/ath_hal/ar5312/ar5312_reset.c

348

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

136

val = OS_REG_READ(ah, AR_STA_ID1);

sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c

139

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

114

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

82

OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5416/ar5416_power.c

94

OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

159

macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

272

OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

390

OS_REG_WRITE(ah, AR_STA_ID1,

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

391

OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

463

reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22));

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

464

OS_REG_WRITE(ah,AR_STA_ID1, reg);

tools/tools/ath/athregs/dumpregs.c

676

OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_CRPT_MIC_ENABLE;

tools/tools/ath/common/dumpregs_5210.c

72

DEFBASICfmt(AR_STA_ID1, "STA_ID1", AR_STA_ID1_BITS),

tools/tools/ath/common/dumpregs_5211.c

236

DEFBASICfmt(AR_STA_ID1, "STA_ID1", AR_STA_ID1_BITS),

tools/tools/ath/common/dumpregs_5212.c

270

DEFBASICfmt(AR_STA_ID1, "STA_ID1",

tools/tools/ath/common/dumpregs_5416.c

306

DEFBASICfmt(AR_STA_ID1, "STA_ID1",