IXGBE_EICR_GPI_SDP0_X540
eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
(eicr & IXGBE_EICR_GPI_SDP0_X540)) {
IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0_X540);
mask |= IXGBE_EICR_GPI_SDP0_X540;
eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
(eicr & IXGBE_EICR_GPI_SDP0_X540)) {
#define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540
#define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540
#define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540