MISC_REG_AEU_GENERAL_ATTN_9
#define MISC_REG_AEU_GENERAL_ATTN_9 \
#define MISC_REG_AEU_GENERAL_ATTN_9 0x008424UL //Access:RW DataWidth:0x1 // Set/clr general attention 9; this will set/clr bit 57 in AEU vector.