MISC_REG_AEU_GENERAL_ATTN_8
#define MISC_REG_AEU_GENERAL_ATTN_8 \
#define MISC_REG_AEU_GENERAL_ATTN_8 0x008420UL //Access:RW DataWidth:0x1 // Set/clr general attention 8; this will set/clr bit 56 in AEU vector.