MISC_REG_AEU_GENERAL_ATTN_7
#define MISC_REG_AEU_GENERAL_ATTN_7 \
#define MISC_REG_AEU_GENERAL_ATTN_7 0x00841cUL //Access:RW DataWidth:0x1 // Set/clr general attention 7; this will set/clr bit 55 in AEU vector.