MISC_REG_AEU_GENERAL_ATTN_5
#define MISC_REG_AEU_GENERAL_ATTN_5 \
#define MISC_REG_AEU_GENERAL_ATTN_5 0x008414UL //Access:RW DataWidth:0x1 // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.