MISC_REG_AEU_GENERAL_ATTN_3
#define MISC_REG_AEU_GENERAL_ATTN_3 \
#define MISC_REG_AEU_GENERAL_ATTN_3 0x00840cUL //Access:RW DataWidth:0x1 // Set/clr general attention 3; this will set/clr bit 51 in AEU vector.