MISC_REG_AEU_GENERAL_ATTN_2
#define MISC_REG_AEU_GENERAL_ATTN_2 \
#define MISC_REG_AEU_GENERAL_ATTN_2 0x008408UL //Access:RW DataWidth:0x1 // Set/clr general attention 2; this will set/clr bit 50 in AEU vector.