MISC_REG_AEU_GENERAL_ATTN_12
#define MISC_REG_AEU_GENERAL_ATTN_12 \
#define MISC_REG_AEU_GENERAL_ATTN_12 0x008430UL //Access:RW DataWidth:0x1 // Set/clr general attention 12; this will set/clr bit 60 in AEU vector.