MISC_REG_AEU_GENERAL_ATTN_11
#define MISC_REG_AEU_GENERAL_ATTN_11 \
#define MISC_REG_AEU_GENERAL_ATTN_11 0x00842cUL //Access:RW DataWidth:0x1 // Set/clr general attention 11; this will set/clr bit 59 in AEU vector.