MISC_REG_AEU_GENERAL_ATTN_10
#define MISC_REG_AEU_GENERAL_ATTN_10 \
#define MISC_REG_AEU_GENERAL_ATTN_10 0x008428UL //Access:RW DataWidth:0x1 // Set/clr general attention 10; this will set/clr bit 58 in AEU vector.