MISC_REG_AEU_GENERAL_ATTN_1
#define MISC_REG_AEU_GENERAL_ATTN_1 \
#define MISC_REG_AEU_GENERAL_ATTN_1 0x008404UL //Access:RW DataWidth:0x1 // Set/clr general attention 1; this will set/clr bit 49 in AEU vector.