sys/dev/drm/amd/display/dc/dce/dce_aux.c

205

REG_UPDATE_2(AUX_SW_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

247

REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);

sys/dev/drm/amd/display/dc/dce/dce_aux.h

34

SRI(AUX_SW_CONTROL, DP_AUX, id), \

sys/dev/drm/amd/display/dc/dce/dce_aux.h

44

uint32_t AUX_SW_CONTROL;

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

235

REG_UPDATE_2(AUX_SW_CONTROL,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

276

REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h

35

SRI(AUX_SW_CONTROL, DP_AUX, id), \

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h

45

uint32_t AUX_SW_CONTROL;

sys/dev/drm/radeon/radeon_dp_auxch.c

113

WREG32(AUX_SW_CONTROL + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

115

WREG32(AUX_SW_CONTROL + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

148

WREG32(AUX_SW_CONTROL + aux_offset[instance],