sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

62

SRII(PHASE, DP_DTO, 0),\

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

63

SRII(PHASE, DP_DTO, 1),\

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

64

SRII(PHASE, DP_DTO, 2),\

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

65

SRII(PHASE, DP_DTO, 3),\

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

66

SRII(MODULO, DP_DTO, 0),\

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

67

SRII(MODULO, DP_DTO, 1),\

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

68

SRII(MODULO, DP_DTO, 2),\

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

69

SRII(MODULO, DP_DTO, 3),\

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

70

SRII(PIXEL_RATE_CNTL, OTG, 0), \

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

71

SRII(PIXEL_RATE_CNTL, OTG, 1), \

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

72

SRII(PIXEL_RATE_CNTL, OTG, 2), \

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

73

SRII(PIXEL_RATE_CNTL, OTG, 3)

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

117

SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

118

SRII(CRTC_H_BLANK_START_END, CRTC, 2), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

119

SRII(BLND_V_UPDATE_LOCK, BLND, 2), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

120

SRII(BLND_CONTROL, BLND, 2), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

43

SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

44

SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

45

SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

46

SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

47

SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

48

SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

52

SRII(BLND_V_UPDATE_LOCK, BLND, 0), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

53

SRII(BLND_V_UPDATE_LOCK, BLND, 1), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

54

SRII(BLND_V_UPDATE_LOCK, BLND, 2), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

55

SRII(BLND_V_UPDATE_LOCK, BLND, 3), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

56

SRII(BLND_V_UPDATE_LOCK, BLND, 4), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

57

SRII(BLND_V_UPDATE_LOCK, BLND, 5), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

58

SRII(BLND_CONTROL, BLND, 0), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

59

SRII(BLND_CONTROL, BLND, 1), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

60

SRII(BLND_CONTROL, BLND, 2), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

61

SRII(BLND_CONTROL, BLND, 3), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

62

SRII(BLND_CONTROL, BLND, 4), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

63

SRII(BLND_CONTROL, BLND, 5)

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

66

SRII(PIXEL_RATE_CNTL, blk, 0), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

67

SRII(PIXEL_RATE_CNTL, blk, 1), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

68

SRII(PIXEL_RATE_CNTL, blk, 2), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

69

SRII(PIXEL_RATE_CNTL, blk, 3), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

70

SRII(PIXEL_RATE_CNTL, blk, 4), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

71

SRII(PIXEL_RATE_CNTL, blk, 5)

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

74

SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

75

SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

76

SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

77

SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

78

SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

79

SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

84

SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

85

SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

86

SRII(CRTC_H_BLANK_START_END, CRTC, 0),\

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

87

SRII(CRTC_H_BLANK_START_END, CRTC, 1),\

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

88

SRII(BLND_V_UPDATE_LOCK, BLND, 0),\

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

89

SRII(BLND_V_UPDATE_LOCK, BLND, 1),\

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

90

SRII(BLND_CONTROL, BLND, 0),\

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

91

SRII(BLND_CONTROL, BLND, 1),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

34

SRII(MPCC_TOP_SEL, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

35

SRII(MPCC_BOT_SEL, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

36

SRII(MPCC_CONTROL, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

37

SRII(MPCC_STATUS, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

38

SRII(MPCC_OPP_ID, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

39

SRII(MPCC_BG_G_Y, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

40

SRII(MPCC_BG_R_CR, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

41

SRII(MPCC_BG_B_CB, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

42

SRII(MPCC_BG_B_CB, MPCC, inst),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

43

SRII(MPCC_SM_CONTROL, MPCC, inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h

46

SRII(MUX, MPC_OUT, inst)