Symbol: SRI
sys/dev/drm/amd/display/dc/dce/dce_abm.h
58
SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
59
SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
60
SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
61
SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
62
SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
63
SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
64
SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
65
SRI(BL1_PWM_USER_LEVEL, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
66
SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
67
SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
sys/dev/drm/amd/display/dc/dce/dce_audio.h
31
SRI(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id),\
sys/dev/drm/amd/display/dc/dce/dce_audio.h
32
SRI(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id),\
sys/dev/drm/amd/display/dc/dce/dce_aux.h
31
SRI(AUX_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/dce/dce_aux.h
32
SRI(AUX_ARB_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/dce/dce_aux.h
33
SRI(AUX_SW_DATA, DP_AUX, id), \
sys/dev/drm/amd/display/dc/dce/dce_aux.h
34
SRI(AUX_SW_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/dce/dce_aux.h
35
SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/dce/dce_aux.h
36
SRI(AUX_SW_STATUS, DP_AUX, id), \
sys/dev/drm/amd/display/dc/dce/dce_clock_source.h
34
SRI(RESYNC_CNTL, PIXCLK, id), \
sys/dev/drm/amd/display/dc/dce/dce_clock_source.h
35
SRI(PLL_CNTL, BPHYC_PLL, id)
sys/dev/drm/amd/display/dc/dce/dce_clock_source.h
38
SRI(RESYNC_CNTL, PIXCLK, id), \
sys/dev/drm/amd/display/dc/dce/dce_clock_source.h
39
SRI(PLL_CNTL, DCCG_PLL, id)
sys/dev/drm/amd/display/dc/dce/dce_clock_source.h
42
SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
sys/dev/drm/amd/display/dc/dce/dce_clock_source.h
61
SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
84
SRI(SETUP, DC_I2C_DDC, id),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
85
SRI(SPEED, DC_I2C_DDC, id),\
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
35
SRI(CUR_UPDATE, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
36
SRI(CUR_CONTROL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
37
SRI(CUR_POSITION, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
38
SRI(CUR_HOT_SPOT, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
39
SRI(CUR_COLOR1, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
40
SRI(CUR_COLOR2, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
41
SRI(CUR_SIZE, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
42
SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
43
SRI(CUR_SURFACE_ADDRESS, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
44
SRI(PRESCALE_GRPH_CONTROL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
45
SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
46
SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
47
SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
48
SRI(INPUT_GAMMA_CONTROL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
49
SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
50
SRI(DC_LUT_RW_MODE, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
51
SRI(DC_LUT_CONTROL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
52
SRI(DC_LUT_RW_INDEX, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
53
SRI(DC_LUT_SEQ_COLOR, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
54
SRI(DEGAMMA_CONTROL, DCP, id)
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
58
SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
sys/dev/drm/amd/display/dc/dce/dce_ipp.h
62
SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
103
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
104
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
105
SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
40
SRI(AUX_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
41
SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
44
SRI(DC_HPD_CONTROL, HPD, id)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
51
SRI(DIG_BE_CNTL, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
52
SRI(DIG_BE_EN_CNTL, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
53
SRI(DP_CONFIG, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
54
SRI(DP_DPHY_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
55
SRI(DP_DPHY_PRBS_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
56
SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
57
SRI(DP_DPHY_SYM0, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
58
SRI(DP_DPHY_SYM1, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
59
SRI(DP_DPHY_SYM2, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
60
SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
61
SRI(DP_LINK_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
62
SRI(DP_LINK_FRAMING_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
63
SRI(DP_MSE_SAT0, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
64
SRI(DP_MSE_SAT1, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
65
SRI(DP_MSE_SAT2, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
66
SRI(DP_MSE_SAT_UPDATE, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
67
SRI(DP_SEC_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
68
SRI(DP_VID_STREAM_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
69
SRI(DP_DPHY_FAST_TRAINING, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
70
SRI(DP_SEC_CNTL1, DP, id)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
74
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
75
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
79
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
84
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
85
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
90
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
91
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
92
SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
97
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
98
SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
35
SRI(GRPH_ENABLE, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
36
SRI(GRPH_CONTROL, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
37
SRI(GRPH_X_START, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
38
SRI(GRPH_Y_START, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
39
SRI(GRPH_X_END, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
40
SRI(GRPH_Y_END, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
41
SRI(GRPH_PITCH, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
42
SRI(HW_ROTATION, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
43
SRI(GRPH_SWAP_CNTL, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
44
SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
45
SRI(GRPH_UPDATE, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
46
SRI(GRPH_FLIP_CONTROL, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
47
SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
48
SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
49
SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
50
SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
51
SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
52
SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
53
SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
54
SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
55
SRI(DMIF_BUFFER_CONTROL, PIPE, id)
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
58
SRI(DVMM_PTE_CONTROL, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
59
SRI(DVMM_PTE_ARB_CONTROL, DCP, id)
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
63
SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
67
SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id)
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
76
SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
77
SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
78
SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\
sys/dev/drm/amd/display/dc/dce/dce_opp.h
44
SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
45
SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
46
SRI(FMT_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
47
SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
48
SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
49
SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
50
SRI(FMT_CLAMP_CNTL, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
51
SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
52
SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
53
SRI(FMT_CLAMP_COMPONENT_B, FMT, id)
sys/dev/drm/amd/display/dc/dce/dce_opp.h
57
SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
58
SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
59
SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
sys/dev/drm/amd/display/dc/dce/dce_opp.h
63
SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
64
SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
65
SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
sys/dev/drm/amd/display/dc/dce/dce_opp.h
69
SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
70
SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
71
SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
sys/dev/drm/amd/display/dc/dce/dce_opp.h
75
SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
76
SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
77
SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \
sys/dev/drm/amd/display/dc/dce/dce_opp.h
78
SRI(CONTROL, FMT_MEMORY, id)
sys/dev/drm/amd/display/dc/dce/dce_opp.h
82
SRI(CONTROL, FMT_MEMORY, id)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
102
SRI(AFMT_CNTL, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
103
SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
104
SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
105
SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
106
SRI(DP_DB_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
107
SRI(DP_MSA_MISC, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
108
SRI(DP_MSA_COLORIMETRY, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
109
SRI(DP_MSA_TIMING_PARAM1, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
110
SRI(DP_MSA_TIMING_PARAM2, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
111
SRI(DP_MSA_TIMING_PARAM3, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
112
SRI(DP_MSA_TIMING_PARAM4, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
113
SRI(HDMI_DB_CONTROL, DIG, id)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
44
SRI(AFMT_AVI_INFO0, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
45
SRI(AFMT_AVI_INFO1, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
46
SRI(AFMT_AVI_INFO2, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
47
SRI(AFMT_AVI_INFO3, DIG, id)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
50
SRI(AFMT_GENERIC_0, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
51
SRI(AFMT_GENERIC_1, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
52
SRI(AFMT_GENERIC_2, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
53
SRI(AFMT_GENERIC_3, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
54
SRI(AFMT_GENERIC_4, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
55
SRI(AFMT_GENERIC_5, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
56
SRI(AFMT_GENERIC_6, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
57
SRI(AFMT_GENERIC_7, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
58
SRI(AFMT_GENERIC_HDR, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
59
SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
60
SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
61
SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
62
SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
63
SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
64
SRI(AFMT_60958_0, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
65
SRI(AFMT_60958_1, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
66
SRI(AFMT_60958_2, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
67
SRI(DIG_FE_CNTL, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
68
SRI(HDMI_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
69
SRI(HDMI_GC, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
70
SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
71
SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
72
SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
73
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
74
SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
75
SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
76
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
77
SRI(HDMI_ACR_32_0, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
78
SRI(HDMI_ACR_32_1, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
79
SRI(HDMI_ACR_44_0, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
80
SRI(HDMI_ACR_44_1, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
81
SRI(HDMI_ACR_48_0, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
82
SRI(HDMI_ACR_48_1, DIG, id),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
83
SRI(TMDS_CNTL, DIG, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
84
SRI(DP_MSE_RATE_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
85
SRI(DP_MSE_RATE_UPDATE, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
86
SRI(DP_PIXEL_FORMAT, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
87
SRI(DP_SEC_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
88
SRI(DP_STEER_FIFO, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
89
SRI(DP_VID_M, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
90
SRI(DP_VID_N, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
91
SRI(DP_VID_STREAM_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
92
SRI(DP_VID_TIMING, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
93
SRI(DP_SEC_AUD_N, DP, id), \
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
94
SRI(DP_SEC_TIMESTAMP, DP, id)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
98
SRI(AFMT_CNTL, DIG, id)
sys/dev/drm/amd/display/dc/dce/dce_transform.h
103
SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
104
SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
sys/dev/drm/amd/display/dc/dce/dce_transform.h
108
SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
109
SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
sys/dev/drm/amd/display/dc/dce/dce_transform.h
39
SRI(LB_DATA_FORMAT, LB, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
40
SRI(GAMUT_REMAP_CONTROL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
41
SRI(GAMUT_REMAP_C11_C12, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
42
SRI(GAMUT_REMAP_C13_C14, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
43
SRI(GAMUT_REMAP_C21_C22, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
44
SRI(GAMUT_REMAP_C23_C24, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
45
SRI(GAMUT_REMAP_C31_C32, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
46
SRI(GAMUT_REMAP_C33_C34, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
47
SRI(OUTPUT_CSC_C11_C12, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
48
SRI(OUTPUT_CSC_C13_C14, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
49
SRI(OUTPUT_CSC_C21_C22, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
50
SRI(OUTPUT_CSC_C23_C24, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
51
SRI(OUTPUT_CSC_C31_C32, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
52
SRI(OUTPUT_CSC_C33_C34, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
53
SRI(OUTPUT_CSC_CONTROL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
54
SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
55
SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
56
SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
57
SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
58
SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
59
SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
60
SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
61
SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
62
SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
63
SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
64
SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
65
SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
66
SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
67
SRI(REGAMMA_LUT_INDEX, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
68
SRI(REGAMMA_LUT_DATA, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
69
SRI(REGAMMA_CONTROL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
70
SRI(DENORM_CONTROL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
71
SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
72
SRI(OUT_ROUND_CONTROL, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
73
SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
74
SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
75
SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
76
SRI(SCL_MODE, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
77
SRI(SCL_TAP_CONTROL, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
78
SRI(SCL_CONTROL, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
79
SRI(SCL_BYPASS_CONTROL, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
80
SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
81
SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
82
SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
83
SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
84
SRI(SCL_COEF_RAM_SELECT, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
85
SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
86
SRI(VIEWPORT_START, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
87
SRI(VIEWPORT_SIZE, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
88
SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
89
SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
90
SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
91
SRI(SCL_VERT_FILTER_INIT, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
92
SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
93
SRI(LB_MEMORY_CTRL, LB, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
94
SRI(SCL_UPDATE, SCL, id), \
sys/dev/drm/amd/display/dc/dce/dce_transform.h
95
SRI(SCL_F_SHARP_CONTROL, SCL, id)
sys/dev/drm/amd/display/dc/dce/dce_transform.h
99
SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
sys/dev/drm/amd/display/dc/dce120/dce120_resource.c
244
SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
100
SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
101
SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
102
SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
103
SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
104
SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
105
SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
106
SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
107
SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
108
SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
109
SRI(CM_MEM_PWR_CTRL, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
110
SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
111
SRI(CM_DGAM_LUT_INDEX, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
112
SRI(CM_DGAM_LUT_DATA, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
113
SRI(CM_CONTROL, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
114
SRI(CM_DGAM_CONTROL, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
115
SRI(CM_TEST_DEBUG_INDEX, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
116
SRI(CM_TEST_DEBUG_DATA, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
117
SRI(FORMAT_CONTROL, CNVC_CFG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
118
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
119
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
120
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
121
SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
122
SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
123
SRI(DPP_CONTROL, DPP_TOP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
124
SRI(CM_HDR_MULT_COEF, CM, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
130
SRI(CM_COMA_C11_C12, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
131
SRI(CM_COMA_C33_C34, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
132
SRI(CM_COMB_C11_C12, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
133
SRI(CM_COMB_C33_C34, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
134
SRI(CM_OCSC_CONTROL, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
135
SRI(CM_OCSC_C11_C12, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
136
SRI(CM_OCSC_C33_C34, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
137
SRI(CM_BNS_VALUES_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
138
SRI(CM_BNS_VALUES_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
139
SRI(CM_BNS_VALUES_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
140
SRI(CM_MEM_PWR_CTRL, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
141
SRI(CM_RGAM_LUT_DATA, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
142
SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
143
SRI(CM_RGAM_LUT_INDEX, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
144
SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
145
SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
146
SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
147
SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
148
SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
149
SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
150
SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
151
SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
152
SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
153
SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
154
SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
155
SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
156
SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
157
SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
158
SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
159
SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
160
SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
161
SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
162
SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
163
SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
164
SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
165
SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
166
SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
167
SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
168
SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
169
SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
170
SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
171
SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
172
SRI(CM_RGAM_CONTROL, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
173
SRI(CM_IGAM_CONTROL, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
174
SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
175
SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
176
SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
177
SRI(CURSOR_CONTROL, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
178
SRI(CM_CMOUT_CONTROL, CM, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
45
SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
46
SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
47
SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
48
SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
49
SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
50
SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
51
SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
52
SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
53
SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
54
SRI(OTG_H_BLANK, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
55
SRI(OTG_V_BLANK, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
56
SRI(SCL_MODE, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
57
SRI(LB_DATA_FORMAT, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
58
SRI(LB_MEMORY_CTRL, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
59
SRI(DSCL_AUTOCAL, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
60
SRI(SCL_BLACK_OFFSET, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
61
SRI(SCL_TAP_CONTROL, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
62
SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
63
SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
64
SRI(DSCL_2TAP_CONTROL, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
65
SRI(MPC_SIZE, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
66
SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
67
SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
68
SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
69
SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
70
SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
71
SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
72
SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
73
SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
74
SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
75
SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
76
SRI(RECOUT_START, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
77
SRI(RECOUT_SIZE, DSCL, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
78
SRI(CM_ICSC_CONTROL, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
79
SRI(CM_ICSC_C11_C12, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
80
SRI(CM_ICSC_C33_C34, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
81
SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
82
SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
83
SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
84
SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
85
SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
86
SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
87
SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
88
SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
89
SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
90
SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
91
SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
92
SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
93
SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
94
SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
95
SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
96
SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
97
SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
98
SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h
99
SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
102
SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
103
SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
104
SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
105
SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
106
SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
111
SRI(PREFETCH_SETTINS, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
112
SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
113
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
114
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
115
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
116
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
117
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
118
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
119
SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
120
SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
121
SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
122
SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
123
SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
124
SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
125
SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
126
SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
129
SRI(CURSOR_SETTINS, HUBPREQ, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
130
SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
131
SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
132
SRI(CURSOR_SIZE, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
133
SRI(CURSOR_CONTROL, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
134
SRI(CURSOR_POSITION, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
135
SRI(CURSOR_HOT_SPOT, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
136
SRI(CURSOR_DST_OFFSET, CURSOR, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
35
SRI(DCHUBP_CNTL, HUBP, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
36
SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
37
SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
38
SRI(DCSURF_TILING_CONFIG, HUBP, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
39
SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
40
SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
41
SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
42
SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
43
SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
44
SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
45
SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
46
SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
47
SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
48
SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
49
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
50
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
51
SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
52
SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
53
SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
54
SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
55
SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
56
SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
57
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
58
SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
59
SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
60
SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
61
SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
62
SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
63
SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
64
SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
65
SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
66
SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
67
SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
68
SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
69
SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
70
SRI(HUBPRET_CONTROL, HUBPRET, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
71
SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
72
SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
73
SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
74
SRI(BLANK_OFFSET_0, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
75
SRI(BLANK_OFFSET_1, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
76
SRI(DST_DIMENSIONS, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
77
SRI(DST_AFTER_SCALER, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
78
SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
79
SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
80
SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
81
SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
82
SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
83
SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
84
SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
85
SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
86
SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
87
SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
88
SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
89
SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
90
SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
91
SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
92
SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
93
SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
94
SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
95
SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
96
SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
97
SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
98
SRI(HUBP_CLK_CNTL, HUBP, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
35
SRI(FORMAT_CONTROL, CNVC_CFG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
36
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
37
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
38
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
39
SRI(CURSOR0_COLOR1, CNVC_CUR, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
43
SRI(CURSOR_SETTINS, HUBPREQ, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
44
SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
45
SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
46
SRI(CURSOR_SIZE, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
47
SRI(CURSOR_CONTROL, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
48
SRI(CURSOR_POSITION, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
49
SRI(CURSOR_HOT_SPOT, CURSOR, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_ipp.h
50
SRI(CURSOR_DST_OFFSET, CURSOR, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
36
SRI(AUX_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
37
SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
40
SRI(DC_HPD_CONTROL, HPD, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
43
SRI(DIG_BE_CNTL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
44
SRI(DIG_BE_EN_CNTL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
45
SRI(TMDS_CTL_BITS, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
46
SRI(DP_CONFIG, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
47
SRI(DP_DPHY_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
48
SRI(DP_DPHY_PRBS_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
49
SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
50
SRI(DP_DPHY_SYM0, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
51
SRI(DP_DPHY_SYM1, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
52
SRI(DP_DPHY_SYM2, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
53
SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
54
SRI(DP_LINK_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
55
SRI(DP_LINK_FRAMING_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
56
SRI(DP_MSE_SAT0, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
57
SRI(DP_MSE_SAT1, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
58
SRI(DP_MSE_SAT2, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
59
SRI(DP_MSE_SAT_UPDATE, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
60
SRI(DP_SEC_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
61
SRI(DP_VID_STREAM_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
62
SRI(DP_DPHY_FAST_TRAINING, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
63
SRI(DP_SEC_CNTL1, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
64
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
65
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
66
SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
37
SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
38
SRI(FMT_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
39
SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
40
SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
41
SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
42
SRI(FMT_CLAMP_CNTL, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
43
SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
44
SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
45
SRI(OPPBUF_CONTROL, OPPBUF, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
46
SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
47
SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.h
48
SRI(OPP_PIPE_CONTROL, OPP_PIPE, id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
35
SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
36
SRI(OTG_VUPDATE_PARAM, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
37
SRI(OTG_VREADY_PARAM, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
38
SRI(OTG_BLANK_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
39
SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
40
SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
41
SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
42
SRI(OTG_H_TOTAL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
43
SRI(OTG_H_BLANK_START_END, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
44
SRI(OTG_H_SYNC_A, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
45
SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
46
SRI(OTG_H_TIMING_CNTL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
47
SRI(OTG_V_TOTAL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
48
SRI(OTG_V_BLANK_START_END, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
49
SRI(OTG_V_SYNC_A, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
50
SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
51
SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
52
SRI(OTG_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
53
SRI(OTG_STEREO_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
54
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
55
SRI(OTG_STEREO_STATUS, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
56
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
57
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
58
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
59
SRI(OTG_TRIGA_CNTL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
60
SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
61
SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
62
SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
63
SRI(OTG_STATUS, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
64
SRI(OTG_STATUS_POSITION, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
65
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
66
SRI(OTG_BLACK_COLOR, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
67
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
68
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
69
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
70
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
71
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
72
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
73
SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
74
SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
75
SRI(CONTROL, VTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
76
SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
77
SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
78
SRI(OTG_GSL_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
79
SRI(OTG_CRC_CNTL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
80
SRI(OTG_CRC0_DATA_RG, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
81
SRI(OTG_CRC0_DATA_B, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
82
SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
83
SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
84
SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
85
SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst)
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
89
SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
90
SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h
91
SRI(OTG_TEST_PATTERN_COLOR, OTG, inst)
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
306
SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
35
SRI(AFMT_CNTL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
36
SRI(AFMT_GENERIC_0, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
37
SRI(AFMT_GENERIC_1, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
38
SRI(AFMT_GENERIC_2, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
39
SRI(AFMT_GENERIC_3, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
40
SRI(AFMT_GENERIC_4, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
41
SRI(AFMT_GENERIC_5, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
42
SRI(AFMT_GENERIC_6, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
43
SRI(AFMT_GENERIC_7, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
44
SRI(AFMT_GENERIC_HDR, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
45
SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
46
SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
47
SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
48
SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
49
SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
50
SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
51
SRI(AFMT_60958_0, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
52
SRI(AFMT_60958_1, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
53
SRI(AFMT_60958_2, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
54
SRI(DIG_FE_CNTL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
55
SRI(HDMI_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
56
SRI(HDMI_DB_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
57
SRI(HDMI_GC, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
58
SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
59
SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
60
SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
61
SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
62
SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
63
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
64
SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
65
SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
66
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
67
SRI(HDMI_ACR_32_0, DIG, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
68
SRI(HDMI_ACR_32_1, DIG, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
69
SRI(HDMI_ACR_44_0, DIG, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
70
SRI(HDMI_ACR_44_1, DIG, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
71
SRI(HDMI_ACR_48_0, DIG, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
72
SRI(HDMI_ACR_48_1, DIG, id),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
73
SRI(DP_DB_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
74
SRI(DP_MSA_MISC, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
75
SRI(DP_MSA_COLORIMETRY, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
76
SRI(DP_MSA_TIMING_PARAM1, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
77
SRI(DP_MSA_TIMING_PARAM2, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
78
SRI(DP_MSA_TIMING_PARAM3, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
79
SRI(DP_MSA_TIMING_PARAM4, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
80
SRI(DP_MSE_RATE_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
81
SRI(DP_MSE_RATE_UPDATE, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
82
SRI(DP_PIXEL_FORMAT, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
83
SRI(DP_SEC_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
84
SRI(DP_STEER_FIFO, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
85
SRI(DP_VID_M, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
86
SRI(DP_VID_N, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
87
SRI(DP_VID_STREAM_CNTL, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
88
SRI(DP_VID_TIMING, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
89
SRI(DP_SEC_AUD_N, DP, id), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
90
SRI(DP_SEC_TIMESTAMP, DP, id)
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
32
SRI(AUX_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
33
SRI(AUX_ARB_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
34
SRI(AUX_SW_DATA, DP_AUX, id), \
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
35
SRI(AUX_SW_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
36
SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
37
SRI(AUX_SW_STATUS, DP_AUX, id), \
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
30
SRI(SETUP, DC_I2C_DDC, id),\
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
31
SRI(SPEED, DC_I2C_DDC, id),\
sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
106
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
117
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
126
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
134
.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
99
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
169
.enable_reg = SRI(reg1, block, reg_num),\
sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
176
.ack_reg = SRI(reg2, block, reg_num),\
sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
187
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
196
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\