sys/dev/drm/amd/display/dc/dce/dce_aux.c

103

AUX_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

111

AUX_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

115

REG_WRITE(AUX_CONTROL, value);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

120

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

126

AUX_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

129

REG_WRITE(AUX_CONTROL, value);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

131

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

94

value = REG_READ(AUX_CONTROL);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

96

AUX_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_aux.h

31

SRI(AUX_CONTROL, DP_AUX, id), \

sys/dev/drm/amd/display/dc/dce/dce_aux.h

41

uint32_t AUX_CONTROL;

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

494

uint32_t addr = AUX_REG(AUX_CONTROL);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

497

set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

498

set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

108

uint32_t AUX_CONTROL;

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

40

SRI(AUX_CONTROL, DP_AUX, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1344

AUX_REG_UPDATE_2(AUX_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

36

SRI(AUX_CONTROL, DP_AUX, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

73

uint32_t AUX_CONTROL;

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

125

value = REG_READ(AUX_CONTROL);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

127

AUX_CONTROL,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

134

AUX_CONTROL,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

142

AUX_CONTROL,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

146

REG_WRITE(AUX_CONTROL, value);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

151

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

157

AUX_CONTROL,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

160

REG_WRITE(AUX_CONTROL, value);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

162

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h

32

SRI(AUX_CONTROL, DP_AUX, id), \

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h

42

uint32_t AUX_CONTROL;

sys/dev/drm/radeon/radeon_dp_auxch.c

104

tmp = RREG32(AUX_CONTROL + aux_offset[instance]);

sys/dev/drm/radeon/radeon_dp_auxch.c

110

WREG32(AUX_CONTROL + aux_offset[instance], tmp);