Symbol: SR
bin/mined/mined.h
387
void SR(int);
bin/mined/mined1.c
1609
case 'a':return(SR);
bin/mined/mined1.c
1616
case 'S': return(SR);
bin/mined/mined1.c
1635
case 'R': return(SR); /* shift-F3 */
sys/dev/drm/amd/display/dc/dce/dce_abm.h
33
SR(BL_PWM_PERIOD_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
34
SR(BL_PWM_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
35
SR(BL_PWM_CNTL2), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
36
SR(BL_PWM_GRP1_REG_LOCK), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
37
SR(LVTMA_PWRSEQ_REF_DIV), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
38
SR(MASTER_COMM_CNTL_REG), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
39
SR(MASTER_COMM_CMD_REG), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
40
SR(MASTER_COMM_DATA_REG1)
sys/dev/drm/amd/display/dc/dce/dce_abm.h
44
SR(DC_ABM1_HG_SAMPLE_RATE), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
45
SR(DC_ABM1_LS_SAMPLE_RATE), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
46
SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
47
SR(DC_ABM1_HG_MISC_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
48
SR(DC_ABM1_IPCSC_COEFF_SEL), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
49
SR(BL1_PWM_CURRENT_ABM_LEVEL), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
50
SR(BL1_PWM_TARGET_ABM_LEVEL), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
51
SR(BL1_PWM_USER_LEVEL), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
52
SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
53
SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
sys/dev/drm/amd/display/dc/dce/dce_abm.h
54
SR(BIOS_SCRATCH_2)
sys/dev/drm/amd/display/dc/dce/dce_audio.h
33
SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
sys/dev/drm/amd/display/dc/dce/dce_audio.h
34
SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
sys/dev/drm/amd/display/dc/dce/dce_audio.h
35
SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
sys/dev/drm/amd/display/dc/dce/dce_audio.h
36
SR(DCCG_AUDIO_DTO_SOURCE),\
sys/dev/drm/amd/display/dc/dce/dce_audio.h
37
SR(DCCG_AUDIO_DTO0_MODULE),\
sys/dev/drm/amd/display/dc/dce/dce_audio.h
38
SR(DCCG_AUDIO_DTO0_PHASE),\
sys/dev/drm/amd/display/dc/dce/dce_audio.h
39
SR(DCCG_AUDIO_DTO1_MODULE),\
sys/dev/drm/amd/display/dc/dce/dce_audio.h
40
SR(DCCG_AUDIO_DTO1_PHASE)
sys/dev/drm/amd/display/dc/dce/dce_aux.h
37
SR(AUXN_IMPCAL), \
sys/dev/drm/amd/display/dc/dce/dce_aux.h
38
SR(AUXP_IMPCAL)
sys/dev/drm/amd/display/dc/dce/dce_clocks.h
37
SR(DENTIST_DISPCLK_CNTL)
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
33
SR(DMCU_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
34
SR(DMCU_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
35
SR(DMCU_RAM_ACCESS_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
36
SR(DMCU_IRAM_WR_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
37
SR(DMCU_IRAM_WR_DATA), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
38
SR(MASTER_COMM_DATA_REG1), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
39
SR(MASTER_COMM_DATA_REG2), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
40
SR(MASTER_COMM_DATA_REG3), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
41
SR(MASTER_COMM_CMD_REG), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
42
SR(MASTER_COMM_CNTL_REG), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
43
SR(DMCU_IRAM_RD_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
44
SR(DMCU_IRAM_RD_DATA), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
45
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
46
SR(SMU_INTERRUPT_CONTROL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
47
SR(DC_DMCU_SCRATCH)
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
50
SR(DMCU_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
51
SR(DMCU_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
52
SR(DMCU_RAM_ACCESS_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
53
SR(DMCU_IRAM_WR_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
54
SR(DMCU_IRAM_WR_DATA), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
55
SR(MASTER_COMM_DATA_REG1), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
56
SR(MASTER_COMM_DATA_REG2), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
57
SR(MASTER_COMM_DATA_REG3), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
58
SR(MASTER_COMM_CMD_REG), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
59
SR(MASTER_COMM_CNTL_REG), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
60
SR(DMCU_IRAM_RD_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
61
SR(DMCU_IRAM_RD_DATA), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
62
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
63
SR(SMU_INTERRUPT_CONTROL), \
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
64
SR(DC_DMCU_SCRATCH)
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
68
SR(DCI_MEM_PWR_STATUS)
sys/dev/drm/amd/display/dc/dce/dce_dmcu.h
72
SR(DMU_MEM_PWR_CNTL)
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
130
SR(DCHUB_FB_LOCATION),\
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
131
SR(DCHUB_AGP_BASE),\
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
132
SR(DCHUB_AGP_BOT),\
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
133
SR(DCHUB_AGP_TOP), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
143
SR(REFCLK_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
144
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
145
SR(DIO_MEM_PWR_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
146
SR(DCCG_GATE_DISABLE_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
147
SR(DCCG_GATE_DISABLE_CNTL2), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
148
SR(DCFCLK_CNTL),\
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
149
SR(DCFCLK_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
150
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
169
SR(DCHUBBUB_SDPIF_FB_BASE),\
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
170
SR(DCHUBBUB_SDPIF_FB_OFFSET),\
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
171
SR(DCHUBBUB_SDPIF_AGP_BASE),\
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
172
SR(DCHUBBUB_SDPIF_AGP_BOT),\
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
173
SR(DCHUBBUB_SDPIF_AGP_TOP),\
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
174
SR(DOMAIN0_PG_CONFIG), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
175
SR(DOMAIN1_PG_CONFIG), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
176
SR(DOMAIN2_PG_CONFIG), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
177
SR(DOMAIN3_PG_CONFIG), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
178
SR(DOMAIN4_PG_CONFIG), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
179
SR(DOMAIN5_PG_CONFIG), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
180
SR(DOMAIN6_PG_CONFIG), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
181
SR(DOMAIN7_PG_CONFIG), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
182
SR(DOMAIN0_PG_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
183
SR(DOMAIN1_PG_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
184
SR(DOMAIN2_PG_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
185
SR(DOMAIN3_PG_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
186
SR(DOMAIN4_PG_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
187
SR(DOMAIN5_PG_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
188
SR(DOMAIN6_PG_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
189
SR(DOMAIN7_PG_STATUS), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
190
SR(D1VGA_CONTROL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
191
SR(D2VGA_CONTROL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
192
SR(D3VGA_CONTROL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
193
SR(D4VGA_CONTROL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
194
SR(VGA_TEST_CONTROL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
195
SR(DC_IP_REQUEST_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
31
SR(LVTMA_PWRSEQ_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
32
SR(LVTMA_PWRSEQ_STATE)
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
49
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
82
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
83
SR(DCFEV_CLOCK_CONTROL), \
sys/dev/drm/amd/display/dc/dce/dce_hwseq.h
92
SR(BLNDV_CONTROL),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
86
SR(DC_I2C_ARBITRATION),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
87
SR(DC_I2C_CONTROL),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
88
SR(DC_I2C_SW_STATUS),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
89
SR(DC_I2C_TRANSACTION0),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
90
SR(DC_I2C_TRANSACTION1),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
91
SR(DC_I2C_TRANSACTION2),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
92
SR(DC_I2C_TRANSACTION3),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
93
SR(DC_I2C_DATA),\
sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.h
94
SR(MICROSECOND_TIME_BASE_DIV)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
47
SR(DMCU_RAM_ACCESS_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
48
SR(DMCU_IRAM_RD_CTRL), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
49
SR(DMCU_IRAM_RD_DATA), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
50
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
76
SR(DCI_MEM_PWR_STATUS)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
86
SR(DCI_MEM_PWR_STATUS)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
93
SR(DCI_MEM_PWR_STATUS)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
99
SR(DCI_MEM_PWR_STATUS)
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
79
SR(DCHUB_FB_LOCATION),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
80
SR(DCHUB_AGP_BASE),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
81
SR(DCHUB_AGP_BOT),\
sys/dev/drm/amd/display/dc/dce/dce_mem_input.h
82
SR(DCHUB_AGP_TOP)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
33
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
34
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
35
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
36
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
37
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
38
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
39
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
40
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
41
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
42
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
43
SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
44
SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
45
SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
46
SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
47
SR(DCHUBBUB_ARB_SAT_LEVEL),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
48
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
49
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
50
SR(DCHUBBUB_TEST_DEBUG_INDEX), \
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
51
SR(DCHUBBUB_TEST_DEBUG_DATA),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
52
SR(DCHUBBUB_SOFT_RESET)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
55
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
56
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
57
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
58
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
59
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
60
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
61
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
62
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
67
SR(DCHUBBUB_SDPIF_FB_TOP),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
68
SR(DCHUBBUB_SDPIF_FB_BASE),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
69
SR(DCHUBBUB_SDPIF_FB_OFFSET),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
70
SR(DCHUBBUB_SDPIF_AGP_BASE),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
71
SR(DCHUBBUB_SDPIF_AGP_BOT),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h
72
SR(DCHUBBUB_SDPIF_AGP_TOP)
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
127
SR(DCHUBBUB_SDPIF_FB_BASE),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.h
128
SR(DCHUBBUB_SDPIF_FB_OFFSET),\
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
38
SR(AUXN_IMPCAL), \
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
39
SR(AUXP_IMPCAL)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
32
SR(DC_I2C_ARBITRATION),\
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
33
SR(DC_I2C_CONTROL),\
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
34
SR(DC_I2C_SW_STATUS),\
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
35
SR(DC_I2C_TRANSACTION0),\
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
36
SR(DC_I2C_TRANSACTION1),\
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
37
SR(DC_I2C_TRANSACTION2),\
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
38
SR(DC_I2C_TRANSACTION3),\
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
39
SR(DC_I2C_DATA),\
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
40
SR(MICROSECOND_TIME_BASE_DIV)
sys/dev/drm/i915/intel_pm.c
2246
I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
sys/dev/drm/i915/intel_pm.c
5679
wm->sr.plane = _FW_WM(tmp, SR);
sys/dev/drm/i915/intel_pm.c
5719
wm->sr.plane = _FW_WM(tmp, SR);
sys/dev/drm/i915/intel_pm.c
873
reg |= FW_WM(wm, SR);
sys/dev/drm/i915/intel_pm.c
937
FW_WM(wm->sr.plane, SR) |
sys/dev/drm/i915/intel_pm.c
987
FW_WM(wm->sr.plane, SR) |
sys/dev/netif/sbsh/if_sbsh.c
384
sc->regs->SR = 0xff;
sys/dev/netif/sbsh/if_sbsh.c
553
if (sc->regs->SR & TXS) {
sys/dev/netif/sbsh/if_sbsh.c
554
sc->regs->SR = TXS;
sys/dev/netif/sbsh/if_sbsh.c
566
u_int8_t status = sc->regs->SR;
sys/dev/netif/sbsh/if_sbsh.c
573
sc->regs->SR = EXT;
sys/dev/netif/sbsh/if_sbsh.c
578
sc->regs->SR = UFL;
sys/dev/netif/sbsh/if_sbsh.c
584
sc->regs->SR = RXS;
sys/dev/netif/sbsh/if_sbsh.c
590
sc->regs->SR = TXS;
sys/dev/netif/sbsh/if_sbsh.c
597
sc->regs->SR = CRC;
sys/dev/netif/sbsh/if_sbsh.c
603
sc->regs->SR = OFL;
sys/dev/netif/sbsh/if_sbsh.c
63
u_int8_t CR, CRB, SR, IMR, CTDR, LTDR, CRDR, LRDR;
sys/dev/netif/sbsh/if_sbsh.c
832
sc->regs->SR = 0xff; /* clear it! */
sys/dev/netif/sbsh/if_sbsh.c
910
sc->regs->SR = 0xff;