sys/dev/drm/i915/intel_ddi.c

1683

pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;

sys/dev/drm/i915/intel_display.c

9147

I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");

sys/dev/drm/i915/intel_dpll_mgr.c

488

I915_WRITE(SPLL_CTL, pll->state.hw_state.spll);

sys/dev/drm/i915/intel_dpll_mgr.c

489

POSTING_READ(SPLL_CTL);

sys/dev/drm/i915/intel_dpll_mgr.c

509

val = I915_READ(SPLL_CTL);

sys/dev/drm/i915/intel_dpll_mgr.c

510

I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);

sys/dev/drm/i915/intel_dpll_mgr.c

511

POSTING_READ(SPLL_CTL);

sys/dev/drm/i915/intel_dpll_mgr.c

541

val = I915_READ(SPLL_CTL);